According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

A subsampling motion detector configured to detect motion information of an object under measurement receives a first wireless radio frequency (RF) signal and transmits a second wireless RF signal, the first wireless RF signal being generated by reflecting the second wireless RF signal from the object. The subsampling motion detector includes a controllable oscillator outputting an oscillation signal, wherein the first wireless RF signal is injected to the controllable oscillator for controlling the controllable oscillator through injecting locking. The subsampling motion detector further including a subsampling phase detector (SSPD) generating a control signal according to the oscillation signal generated by the controllable oscillator and a reference frequency, the SSPD outputting the control signal to the controllable oscillator for controlling the controllable oscillator, the oscillation signal of the controllable oscillator being locked to a multiple of the reference frequency and the control signal representing the motion information of the object.

To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

Performance indicator circuitry is provided for characterizing performance of a phase locked loop (PLL) in a phase path of a polar modulator or polar transmitter that is used to generate a phase modulated RF signal. The PLL includes an oscillator, a high pass path, and a low pass path. The low pass path includes a loop filter. The performance indicator circuitry includes first input circuitry and parameter calculation circuitry. The first input circuitry is configured to input a loop filter signal from the loop filter. The parameter calculation circuitry is configured to compute a value for a performance indicator based on the loop filter signal and control or characterize an aspect of operation of the PLL based on the value.

In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.

One or more examples relate to an apparatus includes an error detector, an oscillator, an analog proportional path, and a digital integral path. The oscillator includes an analog proportional input, a digital integral input, and an analog integral input. The analog proportional path to provide a control signal for the analog proportional input of the oscillator. The digital integral path to provide a control for the digital integral input and the analog integral input of the oscillator. A first signal path of an interface includes a direct coupling between the digital phase detector and integrator and the digital integral input of the oscillator. A second signal path of the interface includes a digital-to-analog converter (DAC) with a filtered delta-sigma modulator (DSM) input between the digital phase detector and integrator and the analog integral input of the oscillator.

One or more examples relate to an apparatus includes an error detector, an oscillator, an analog proportional path, and a digital integral path. The oscillator includes an analog proportional input, a digital integral input, and an analog integral input. The analog proportional path to provide a control signal for the analog proportional input of the oscillator. The digital integral path to provide a control for the digital integral input and the analog integral input of the oscillator. A first signal path of an interface includes a direct coupling between the digital phase detector and integrator and the digital integral input of the oscillator. A second signal path of the interface includes a digital-to-analog converter (DAC) with a filtered delta-sigma modulator (DSM) input between the digital phase detector and integrator and the analog integral input of the oscillator.

In a reference signal generator including a synchronization circuit configured to convert a digital signal into an analog signal, supply this signal to a voltage controlled oscillator, and control the voltage controlled oscillator to obtain a signal synchronized with the reference signal, without an accumulation of quantization error in a holdover control in which an acquisition of a reference signal is not available. The reference signal generator includes a phase synchronization circuit and a controller. The phase synchronization circuit controls the reference signal outputted from the oscillator, according to a control signal obtained based on the reference signal. The controller generates a free-running control signal and controls the oscillator when the reference signal becomes unavailable. The oscillator receives discrete values and oscillates accordingly. A digital delta-sigma modulator configured to modulate the free-running control signal of the controller disposed in a subsequent stage of the controller.

In a reference signal generator including a synchronization circuit configured to convert a digital signal into an analog signal, supply this signal to a voltage controlled oscillator, and control the voltage controlled oscillator to obtain a signal synchronized with the reference signal, without an accumulation of quantization error in a holdover control in which an acquisition of a reference signal is not available. The reference signal generator includes a phase synchronization circuit and a controller. The phase synchronization circuit controls the reference signal outputted from the oscillator, according to a control signal obtained based on the reference signal. The controller generates a free-running control signal and controls the oscillator when the reference signal becomes unavailable. The oscillator receives discrete values and oscillates accordingly. A digital delta-sigma modulator configured to modulate the free-running control signal of the controller disposed in a subsequent stage of the controller.