Embodiments of the invention may provide a phase locked loop (PLL) for a long-range and short-range frequency-modulated carrier-frequency (FMCW) RADAR system, including: a single feedback loop for generating a control signal based on differences between an output signal of the RADAR and a reference signal; a first voltage-controlled oscillator (VCO) adapted to generate a first output signal having a first loop bandwidth using the control signal; a second VCO adapted to generate a second output signal having a second loop bandwidth using the control signal; and an output switch for selecting one of the first output signal and the second output signal and outputting the selected signal as the output signal of the RADAR.

Methods and apparatus for quickly changing line rates in PCIe analyzers without resetting the receivers. One example circuit for multi-rate reception generally includes: a receiver having a data input, a data output, and a clock input configured to receive a clock signal from a clock generator, the receiver being configured to switch between receiving data at a first data rate and at least one second data rate and to sample data according to the first data rate, wherein the first data rate is higher than the at least one second data rate; a phase detector having an input coupled to the data output of the receiver; and a filter having an input coupled to an output of the phase detector and having an output configured to effectively control a phase of the sampling by the receiver when the data is at the at least one second data rate.

A DLL includes a delay line with two phase outputs, a gater coupled with the delay line phase outputs, a PFD coupled with gater outputs, a PD coupled with PFD outputs, a retimer coupled with PD outputs, and a loop filter with inputs coupled with the retimer and a speed control output coupled with the delay line. The gater passes signals on its two inputs to its two outputs, apart from a first pulse on its first input. The PD determines if the second gated signal leads or lags the first gated signal. The retimer retimes PD output signals to be aligned with a delay line input signal. The loop filter uses the retimed PD output signals to determine if the delay line should delay more or delay less, and outputs a speed control signal to control the delay line speed.

A DLL includes a delay line with two phase outputs, a gater coupled with the delay line phase outputs, a PFD coupled with gater outputs, a PD coupled with PFD outputs, a retimer coupled with PD outputs, and a loop filter with inputs coupled with the retimer and a speed control output coupled with the delay line. The gater passes signals on its two inputs to its two outputs, apart from a first pulse on its first input. The PD determines if the second gated signal leads or lags the first gated signal. The retimer retimes PD output signals to be aligned with a delay line input signal. The loop filter uses the retimed PD output signals to determine if the delay line should delay more or delay less, and outputs a speed control signal to control the delay line speed.

A division factor generator of a feedback divider block in a fractional-N phase locked loop (PLL). The division factor generator is enabled to operate with larger values of division factors without increased complexity of an internal modulator core implemented, for example, as a delta-sigma modulator (DSM) having a signal transfer function (STF), wherein the STF always generates only an integer value as an output in response to an integer value received as input.

A division factor generator of a feedback divider block in a fractional-N phase locked loop (PLL). The division factor generator is enabled to operate with larger values of division factors without increased complexity of an internal modulator core implemented, for example, as a delta-sigma modulator (DSM) having a signal transfer function (STF), wherein the STF always generates only an integer value as an output in response to an integer value received as input.

The technology of this application relates to a phase-locked loop circuit that includes a phase frequency detector, a first voltage control module, a second voltage control module, a third voltage control module, a voltage-controlled oscillator, and a frequency divider. A first output end of the phase frequency detector is connected to a first input end of the first voltage control module and a first input end of the second voltage control module, a second output end of the phase frequency detector is connected to a second input end of the first voltage control module and a second input end of the second voltage control module, an output end of the first voltage control module.

Phase Locked Loop, PLL, circuitry comprising a phase detector configured to generate a first pulse signal comprising at least one first pulse, a property of each first pulse being indicative of a phase difference between a reference signal and a feedback signal; a pulse repeater circuit configured, based on the first pulse signal, to generate a second pulse signal comprising, for each first pulse, a second pulse generated by repeating the corresponding first pulse; and an oscillator configured to generate the feedback signal and control a frequency of the feedback signal based on the second pulse signal.

A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.

A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.