A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.

The present disclosure provides a circuit and method for expanding the lock range of injection-locked oscillators. The circuit includes N injection-locked oscillators and a lock detector, where the lock detector includes an alignment monitor, a clock selector, and N self-samplers. A pulse reference signal is inputted into the N injection-locked oscillators, and the output of each injection-locked oscillator is connected to the clock selector and the corresponding self-sampler. The self-samplers sample the outputs of the N injection-locked oscillators and output the sampling results to the alignment monitor. The alignment monitor monitors the sampling results, determines the locking conditions of the injection-locked oscillators, and turns off the unlocked oscillators. The clock selector selects a locked oscillator and transmits the output of the locked oscillator as a system lock.

The present disclosure provides a circuit and method for expanding the lock range of injection-locked oscillators. The circuit includes N injection-locked oscillators and a lock detector, where the lock detector includes an alignment monitor, a clock selector, and N self-samplers. A pulse reference signal is inputted into the N injection-locked oscillators, and the output of each injection-locked oscillator is connected to the clock selector and the corresponding self-sampler. The self-samplers sample the outputs of the N injection-locked oscillators and output the sampling results to the alignment monitor. The alignment monitor monitors the sampling results, determines the locking conditions of the injection-locked oscillators, and turns off the unlocked oscillators. The clock selector selects a locked oscillator and transmits the output of the locked oscillator as a system lock.

Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.

Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.

A digital phase-locked loop (PLL) includes a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO). The DCO generates a PLL clock signal and various sampling clock signals that are mesochronous. The TDC samples a phase difference between a reference clock signal and a frequency-divided version of the PLL clock signal based on the sampling clock signals and various enable signals. The enable signals are generated based on a calibration of the digital PLL. Each enable signal is associated with a sampling clock signal and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference. Further, the TDC generates control data indicative of the sampled phase difference. The DCO generates the PLL clock signal and the sampling clock signals based on the control data until the digital PLL is in a phase-locked state.

A digital phase-locked loop (PLL) includes a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO). The DCO generates a PLL clock signal and various sampling clock signals that are mesochronous. The TDC samples a phase difference between a reference clock signal and a frequency-divided version of the PLL clock signal based on the sampling clock signals and various enable signals. The enable signals are generated based on a calibration of the digital PLL. Each enable signal is associated with a sampling clock signal and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference. Further, the TDC generates control data indicative of the sampled phase difference. The DCO generates the PLL clock signal and the sampling clock signals based on the control data until the digital PLL is in a phase-locked state.

A time to digital converter has a counter, a first phase difference detector, a first capacitor, a second capacitor having capacitance N times a capacitance of the first capacitor, a comparator to compare a charge voltage of the first capacitor with a charge voltage of the second capacitor, a first charge controller, a first phase difference arithmetic unit, a second phase difference detector, a second charge controller, a second phase difference arithmetic unit to operate the phase difference between the first signal and the second signal, and a third phase difference arithmetic unit to detect a fractional phase difference between the first signal and the second signal. The first phase difference arithmetic unit operates the phase difference between the first signal and the second signal, based on a reference phase, when the counter suspends a measurement operation.

A time to digital converter has a counter, a first phase difference detector, a first capacitor, a second capacitor having capacitance N times a capacitance of the first capacitor, a comparator to compare a charge voltage of the first capacitor with a charge voltage of the second capacitor, a first charge controller, a first phase difference arithmetic unit, a second phase difference detector, a second charge controller, a second phase difference arithmetic unit to operate the phase difference between the first signal and the second signal, and a third phase difference arithmetic unit to detect a fractional phase difference between the first signal and the second signal. The first phase difference arithmetic unit operates the phase difference between the first signal and the second signal, based on a reference phase, when the counter suspends a measurement operation.

A phase locked loop is disclosed comprising: a phase detector, a loop filter, a frequency controller oscillator and a lock detector. The phase detector is operable in a bang-bang mode to provide a binary phase error signal indicating whether there is a positive or negative phase difference between a reference signal and a feedback signal. The loop filter is configured to provide a control signal derived from the binary phase error signal. The frequency controlled oscillator is configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal. The lock/unlock detector is configured to determine a lock/unlock state of the phase locked loop, the lock/unlock state derived from a duty cycle and/or spectral content of the binary phase error signal.