A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.

A built-in self-test (BIST) block is provided that is incorporated into an all-digital phase locked loop (ADPLL) located on chip with the ADPLL. The BIST performs testing functions without need for support external to the chip. Test setup, test control, and test evaluation are performed entirely on chip. The BIST provides information regarding success or failure of the testing and can provide error information regarding test cases that do not pass successfully.

A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.

A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.

Disclosed is a phase-locked loop circuit, including: a phase-locked loop, a locking detection circuit, an input end for inputting a reference clock signal, a first output end for outputting an oscillator clock signal, and a second output end for outputting a locking signal, wherein the phase-locked loop is configured to output the oscillator clock signal according to the reference clock signal and control the reference clock signal and the oscillator clock signal to be synchronous; and the locking detection circuit is configured to output the locking signal to the second output end when the oscillator clock signal and the reference clock signal are synchronous.

Disclosed is a phase-locked loop circuit, including: a phase-locked loop, a locking detection circuit, an input end for inputting a reference clock signal, a first output end for outputting an oscillator clock signal, and a second output end for outputting a locking signal, wherein the phase-locked loop is configured to output the oscillator clock signal according to the reference clock signal and control the reference clock signal and the oscillator clock signal to be synchronous; and the locking detection circuit is configured to output the locking signal to the second output end when the oscillator clock signal and the reference clock signal are synchronous.

Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.

Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.

Methods and systems are described for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval, generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval, comparing the first and the second early-late vote measurements, and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote measurements are within a predetermined threshold.

A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.