A clock signal generating circuit includes a detecting circuit configured to generate a first voltage based on first and second clock signals and adjust a level of the first voltage in response to first and second setup voltages and a resistance variable code, a comparing circuit configured to compare the first voltage and a reference voltage and output a check signal according to a comparison result, a code generating circuit configured to perform a first modulation operation for determining the resistance variable code in response to the check signal and perform a second modulation operation for determining a control code in response to the check signal, and an oscillator configured to adjust an amplitude of the first and second clock signals in response to the control code, and output the first and second clock signals having the adjusted amplitude.

A clock signal generating circuit includes a detecting circuit configured to generate a first voltage based on first and second clock signals and adjust a level of the first voltage in response to first and second setup voltages and a resistance variable code, a comparing circuit configured to compare the first voltage and a reference voltage and output a check signal according to a comparison result, a code generating circuit configured to perform a first modulation operation for determining the resistance variable code in response to the check signal and perform a second modulation operation for determining a control code in response to the check signal, and an oscillator configured to adjust an amplitude of the first and second clock signals in response to the control code, and output the first and second clock signals having the adjusted amplitude.

Power consumption of a time-to-digital converter (TDC) used in a phase locked loop (ADPLL) is suppressed. The time-to-digital converter includes an analog-to-digital converter and a current source circuit. The analog-to-digital converter includes a predetermined charge capacitor. The current source circuit supplies a charge current that charges the charge capacitor of the analog-to-digital converter with a charge. The charge current supplied by the current source circuit is supplied so that a charge voltage at the time of charging the charge capacitor of the analog-to-digital converter with the charge current has a constant gradient with respect to a charge time.

The present invention provides a clock source for an integrated circuit, comprising a primary oscillator adapted to generate a primary clock signal based on a reference control signal, at least one secondary oscillator each secondary oscillator being adapted to generate a secondary clock signal based on the reference control signal, wherein for each secondary oscillator a frequency correction unit is provided and adapted to adjust the reference control signal for the associated secondary oscillator based on the primary clock signal and the secondary clock signal of the associated secondary oscillator such that the clock frequency of the secondary clock signal of the associated secondary oscillator essentially equals the clock frequency of the primary clock signal. The present invention furthermore provides a method for providing a clock signal, and an integrated circuit.

The present invention provides a clock source for an integrated circuit, comprising a primary oscillator adapted to generate a primary clock signal based on a reference control signal, at least one secondary oscillator each secondary oscillator being adapted to generate a secondary clock signal based on the reference control signal, wherein for each secondary oscillator a frequency correction unit is provided and adapted to adjust the reference control signal for the associated secondary oscillator based on the primary clock signal and the secondary clock signal of the associated secondary oscillator such that the clock frequency of the secondary clock signal of the associated secondary oscillator essentially equals the clock frequency of the primary clock signal. The present invention furthermore provides a method for providing a clock signal, and an integrated circuit.

A frequency adjusting apparatus used in a processing chip operated at an operation frequency according to a power is provided that includes a clock supplying circuit, a frequency division circuit and a control circuit. The clock supplying circuit outputs one of clock signals as a supplied clock signal. The frequency division circuit performs frequency division on the supplied clock signal according to a parameter to generate an output clock signal. The control circuit determines a combination of a selected clock signal and a value of the parameter for gradually increasing the frequency of the output clock signal during the increasing of the voltage value that passes through voltage value sections, wherein when the voltage value is determined to be larger than a second threshold value and when the voltage value sections correspond to higher voltage values, the selected clock signal has a higher frequency.

A frequency adjusting apparatus used in a processing chip operated at an operation frequency according to a power is provided that includes a clock supplying circuit, a frequency division circuit and a control circuit. The clock supplying circuit outputs one of clock signals as a supplied clock signal. The frequency division circuit performs frequency division on the supplied clock signal according to a parameter to generate an output clock signal. The control circuit determines a combination of a selected clock signal and a value of the parameter for gradually increasing the frequency of the output clock signal during the increasing of the voltage value that passes through voltage value sections, wherein when the voltage value is determined to be larger than a second threshold value and when the voltage value sections correspond to higher voltage values, the selected clock signal has a higher frequency.

A receiving device includes a phase-locked loop (PLL) circuit having a current control oscillator, a phase detector, an integral path, and a proportional path. The current control oscillator can generate an oscillation clock based on a first and second current. The phase detector can acquire a phase detection result based on the oscillation clock and a received signal. The integral path can generate the first current based on an integrated value of the phase detection results and supply the first current to the current control oscillator. The proportional path includes a digital-to-current converter to generate the second current based on the phase detection result and supply the second current to the current control oscillator. The receiving device includes a controller configured to adjust the second current based on frequency-current characteristics of the current control oscillator.

A receiving device includes a phase-locked loop (PLL) circuit having a current control oscillator, a phase detector, an integral path, and a proportional path. The current control oscillator can generate an oscillation clock based on a first and second current. The phase detector can acquire a phase detection result based on the oscillation clock and a received signal. The integral path can generate the first current based on an integrated value of the phase detection results and supply the first current to the current control oscillator. The proportional path includes a digital-to-current converter to generate the second current based on the phase detection result and supply the second current to the current control oscillator. The receiving device includes a controller configured to adjust the second current based on frequency-current characteristics of the current control oscillator.

An embodiment method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.