A clock and data recovery circuit is disclosed. The clock and data recovery circuit includes a phase detection circuit, a first voting circuit, a low-pass filtering circuit and a phase interpolation circuit. The phase detection circuit is configured to receive a first signal and a clock signal and generate a phase signal. The first voting circuit is configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result. The low-pass filtering circuit is configured to generate a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal.

A method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller, comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

A method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller, comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

A variable-frequency oscillator generates an oscillator clock having a frequency that corresponds to a control signal. A programmable frequency divider divides the oscillator clock, so as to generate a divided clock. A F/V converter circuit includes a capacitor and a switch that switches at a frequency that corresponds to the divided clock, and generates a detection voltage that corresponds to a reference current. A reference voltage source outputs a reference voltage that corresponds to the electric potential that occurs at the resistor due to a reference current. A feedback circuit adjusts a control signal such that the detection voltage approaches the reference voltage. A correction circuit changes the frequency-dividing ratio of the programmable frequency divider based on a modulation signal modulated according to a correction coefficient that corresponds to the temperature.

A frequency variable oscillator generates a clock having a frequency according to a control signal. A reference current source generates a reference current. A path selector distributes the reference current to a first path and a second path in a time-sharing manner in synchronization with the clock. An F/V conversion circuit includes a capacitor connected to the first path, and charges or discharges the capacitor with the reference current and generates a detection voltage. The reference voltage source includes a resistor connected to the second path, and outputs a reference voltage according to a voltage across the resistor. A feedback circuit adjusts a control signal so that the detection voltage approaches the reference voltage.

A circuit includes a phase-locked loop configured to receive a reference clock signal and to generate a first clock signal having a first frequency. A secondary clock generation circuit is configured to generate a second clock signal having a second frequency lower than the first frequency. A voltage detection circuit is coupled to receive a supply voltage and configured to detect a droop in the supply voltage and generate a clock control signal in response to detecting a droop in the supply voltage. A selection circuit is coupled to the voltage detection circuit to receive the clock control signal and is configured to select one of the first clock signal and the second clock signal based on the clock control signal.

A circuit includes a phase-locked loop configured to receive a reference clock signal and to generate a first clock signal having a first frequency. A secondary clock generation circuit is configured to generate a second clock signal having a second frequency lower than the first frequency. A voltage detection circuit is coupled to receive a supply voltage and configured to detect a droop in the supply voltage and generate a clock control signal in response to detecting a droop in the supply voltage. A selection circuit is coupled to the voltage detection circuit to receive the clock control signal and is configured to select one of the first clock signal and the second clock signal based on the clock control signal.

A clock and data recovery circuit is disclosed. The clock and data recovery circuit includes a phase detection circuit, a first voting circuit, a low-pass filtering circuit and a phase interpolation circuit. The phase detection circuit is configured to receive a first signal and a clock signal and generate a phase signal. The first voting circuit is configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result. The low-pass filtering circuit is configured to generate a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal.

Provided herein are gap detection and compensation schemes for timing alignment systems. In certain embodiments, a timing alignment system includes a detector that generates one or more loop control signals based on comparing a reference clock signal to a feedback clock signal, a loop filter having a loop voltage that is adjusted based on the one or more loop control signals, and a gap detection and compensation circuit that processes the one or more loop control signals to detect a gap in at least one of the reference clock signal or the feedback clock signal. In response to detecting the gap, the gap detection and compensation circuit modifies the one or more loop control signals to provide an adjustment to the loop voltage.

Provided herein are gap detection and compensation schemes for timing alignment systems. In certain embodiments, a timing alignment system includes a detector that generates one or more loop control signals based on comparing a reference clock signal to a feedback clock signal, a loop filter having a loop voltage that is adjusted based on the one or more loop control signals, and a gap detection and compensation circuit that processes the one or more loop control signals to detect a gap in at least one of the reference clock signal or the feedback clock signal. In response to detecting the gap, the gap detection and compensation circuit modifies the one or more loop control signals to provide an adjustment to the loop voltage.