A digital PLL circuitry, according to the present embodiment, includes: a phase difference arithmetic circuitry configured to arithmetically operate and output a phase difference between an input clock signal and an output clock signal; a first control code generation circuitry configured to generate a first control code for controlling an oscillation frequency based on the phase difference and a frequency control input being a control target frequency relating to the output clock signal, and output the first control code; a second control code generation circuitry configured to generate and output a second control code for controlling the oscillation frequency according to a sequence; a selection circuitry configured to select and output one of the first control code and the second control code as a selection control code; and a digitally controlled oscillator configured to output the output clock signal of the oscillation frequency according to the selection control code.

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

The present disclosure relates to a digital subsampling phase-locked-loop (PLL) with a digital-to-time converter (DTC) based successive-approximation-register (SAR) phase estimation. This disclosed PLL utilizes a DTC and a one-bit sampler to generate one phase word by calculating multiple one-bit phase measurements with a SAR algorithm. The one phase word, which indicates the phase estimation of a radio frequency (RF) output signal compared to a reference signal, enables the PLL to lock the RF output signal with the reference signal in a short settling time. In addition, utilizing the one-bit sampler instead of a conventional frequency divider is good for linearity and low power consumption of the PLL without introducing significant noise in the RF output signal.

Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

An oscillator control system includes an non-linear oscillator structure configured to oscillate about an axis; a driver circuit configured to generate a driving signal to drive the oscillator structure; a detection circuit configured to measure an angle amplitude and a phase error of the oscillator structure; an amplitude controller configured to generate a reference oscillator period based on the measured angle amplitude; a period and phase controller configured to receive the reference oscillator period and the measured phase error from the detection circuit, generate at least one control parameter of the driving signal based on the reference oscillator period and the measured phase error, and determine a driving period of the driving signal based on the reference oscillator period and the measured phase error. The driver circuit is configured to generate the driving signal based on the at least one control parameter and the driving period.

Methods and digital circuits providing frequency correction to frequency synthesizers are disclosed. An FLL digital circuit is provided that is configured to handle a reference frequency that is dynamic and ranges over a multi-decade range of frequencies. The FLL circuit includes a digital frequency iteration engine that allows for detection of disappearance of a reference frequency. When the digital frequency iteration engine detects that the reference frequency signal is not available, the oscillator generated frequency is not corrected, and the last value of the oscillator generated frequency is held until the reference frequency signal becomes available again. This FLL circuit is also preceded by a low-pass filter which is dynamically tuned to the frequency to which the FLL locks, eliminating harmonic components in the original signal which might otherwise cause errors in frequency estimation.

The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.

The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.

An all-digital phase-locked loop (ADPLL) circuit and a calibration method thereof are provided. The ADPLL circuit includes a digitally controlled oscillator (DCO) circuit, a phase detector circuit, and a calibration circuit coupled between the DCO circuit and the phase detector circuit. The DCO circuit generates a clock signal according to a frequency control signal. The phase detector circuit generates a phase error value according to a reference signal and the clock signal. More particularly, after the ADPLL circuit performs a locking operation for a period of time, the frequency control signal is tied at a locked value which is obtained when the ADPLL circuit performs the locking operation, and the calibration circuit may modify a current of at least one current source within the DCO circuit according to the phase error value.

An all-digital-phase-locked-loop (ADPLL) includes a digitally controlled oscillator (DCO) arranged to generate a DCO output signal, and a feedback loop comprising a set of components for controlling the DCO. The set of components comprise: a time-to-digital converter (TDC) arranged to generate a TDC output code indicative of the phase difference between the reference signal and the enable signal measured within the predetermined observation window; a subset of components arranged to generate the enable signal from the DCO output signal; and an offset calibration system connected to the TDC output, which when activated is arranged to evaluate the difference between the first and second offset delay values by monitoring the TDC output code generated over a predetermined period of time, and to adjust the difference to position the predetermined observation window with respect to the reference signal.