A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.

A system may include a digitally-controlled oscillator configured to generate an output clock signal based on a control signal received at an input of the digitally-controlled oscillator and a control circuit configured to calculate an error signal between the output clock signal and an external reference clock signal, filter the error signal to generate a correction signal, generate the control signal based on the correction signal, and switch between a first mode of operation and a second mode of operation without artifacts on the correction signal during switching between the first mode and the second mode.

A real-time clock module includes: an oscillation circuit configured to generate a first clock signal by oscillating a resonator; an interface circuit configured to receive alarm setting data; a memory in which the alarm setting data and a program are to be stored; and a processor configured to execute the program to perform a comparison process of comparing clocking data generated based on the first clock signal with the alarm setting data, and output an alarm signal according to a result of the comparison process.

A device for providing side-channel protection to a data processing circuit is provided and includes a chaotic oscillator and a counter. The data processing circuit has an input for receiving an input signal, a power supply terminal, and an output for providing an output signal. The chaotic oscillator circuit has an input coupled to receive a control signal, and an output coupled to provide an output signal for controlling a voltage level of a power supply voltage of the data processing circuit. The counter has an input coupled to receive a clock signal, and an output coupled to control a variable parameter of the chaotic oscillator in response to the clock signal. In another embodiment, a method is provided providing the side-channel protection to the device.

A signal generating electric circuit, a signal generating method, a digit-to-time converting electric circuit and a digit-to-time converting method. The signal generating electric circuit includes: a first generating electric circuit configured for, based on a first frequency control word and a reference time unit, generating a periodic first output signal; and a second generating electric circuit configured for, based on a second frequency control word and the reference time unit, generating a periodic second output signal. The first frequency control word includes a first integer part and a first fractional part, the second frequency control word includes a second integer part and a second fractional part, the first integer part is equal to the second integer part, the first fractional part and the second fractional part are not equal, and a period of the first output signal and a period of the second output signal are not equal.

A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected parallel to the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at start up based on an interpolated frequency value obtained prior to start up. Faster settling is provided with less complex algorithms.

The application discloses a transmitter with self-interference calibration ability, including: a signal generation unit for generating a signal; a CORDIC for generating an amplitude modulation signal and a phase modulation signal according to the signal; phase processing unit, for generating a frequency signal according to the phase modulation signal; a DPLL, including: a DCO, self-interference calibration unit, for generating phase compensation according to the signal, a phase difference and a reference clock; and a DCO control generation unit; and an output unit, for generating an output signal according to the amplitude modulation signal and a DCO output signal.

A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.

A tracking system for a digital Phase Locked Loop (PLL), the tracking system including a PLL model configured to emulate an actual internal PLL signal, wherein the emulation is based on another internal PLL signal received from the digital PLL and on an estimated analog PLL parameter of the PLL model; and a tracker configured to compare the emulated internal PLL signal with the actual internal PLL signal, and to update the estimated analog PLL parameter according to a minimization algorithm that minimizes a result of the comparison.

An oscillator and a clock circuit are disclosed. In an oscillator (100), a tail inductor connected to a cross-coupled transistor includes at least two inductors connected in parallel. Therefore, an inductance of the tail inductor is less than an inductance of any one of the inductors. This can address a design difficulty that a tail inductor with a smaller inductance needs to be used as an operating frequency of a VCO increases. The oscillator (100) includes a first cross-coupled transistor (121) and a first tail inductor (111). The first tail inductor (111) includes at least two inductors connected in parallel. The first tail inductor (111) is coupled to a source of the first cross-coupled transistor (121). The source of the first cross-coupled transistor (121) is coupled to a power supply or a ground through the first tail inductor (111).