A dual-loop phase-locking circuit combines a conventional phase-frequency-detector (PFD) and frequency-divider based first loop to lock an output signal frequency to a multiple of a reference signal frequency within a first loop bandwidth BW1 with a second loop to simultaneously lock the output signal phase to a second signal independently locked to the same multiple of the reference signal. The second loop integrates the phase error between the output signal and the second signal, and applies an offset at the PFD output in the first loop to reduce the first loop phase errors within a second loop bandwidth BW2 (<BW1). The first loop bandwidth BW1 can be optimized for overall phase-noise performance of the output signal while retaining the excellent capture and hold characteristics of that loop's topology. The second loop provides superior carrier-frequency phase alignment between the output signal and second signal. The output and second signal may therefore be configured as inputs to systems that require highly coherent carrier signals with de-correlated phase-noise such as phase-noise measurement systems or phase-noise cancellation systems.

Circuits and methods involve an integrated circuit (IC) device, a plurality of application-specific sub-circuits, and a plurality of instances of a measuring circuit. The application-specific sub-circuits are disposed within respective areas of the IC device. Each instance of the measuring circuit is associated with one of the application-specific sub-circuits and is disposed within a respective one of the areas of the device. Each instance of the measuring circuit further includes a ring oscillator and a register for storage of a value indicative of an interval of time. Each instance of the measuring circuit is configured to measure passage of the interval of time based on a first clock signal, count oscillations of an output signal of the ring oscillator during the interval of time, and output a value indicating a number of oscillations counted during the interval of time.

An electronic device comprises a regulator, and an oscillator and a resistor coupled to the regulator. The electronic device further comprises a feedback controller that includes a differential amplifier coupled between the oscillator, the resistor, and the regulator. The feedback controller is configured to apply a control voltage to the regulator in response to a resistor voltage upon the resistor and an oscillator voltage upon the oscillator. The feedback controller can be coupled to control a substantially equal voltage upon the resistor and the oscillator.

A digital-to-time converter (DTC)-based open loop frequency synthesis and calibration circuit may be used to provide a precise clock signal. The DTC calibration circuit may include a DTC to generate a DTC clock signal based on a received input clock frequency and a received initial digital input code, a phase-lock loop (PLL) to generate a PLL clock signal based on a received PLL input, a binary phase-detector (PD) to generate a PD output based on a comparison between the DTC clock signal and the PLL clock signal, a plurality of calibration bins to generate a signed accumulated PD portion based on the PD output, and an adder to generate a calibrated DTC input code based on a combination of the signed accumulated PD portion and a subsequent digital input code, where the DTC generates a calibrated clock signal based on the calibrated DTC input code.

The data recovery from sub-carriers gradients (DRSG) of a received OFDM signal affected by deterministic and random distortions introduced by a transmission link, contributes a method and a circuit for utilizing gradients characterizing shapes of OFDM sub-carriers comprised in such OFDM signal for recovering data symbols transmitted originally.

A system includes a ring oscillator including an odd number of inverters arranged in a ring. The system also includes a time to digital converter including an odd number of flops, where each of the flops is coupled to an output of a different inverter. The system includes a level shifter coupled to the inverters and to the flops. The system also includes a Gray counter coupled to at least one of the flops. The system includes a decoder coupled to the time to digital converter. The system also includes a phase frequency detector coupled to the decoder.

Provided are a clock signal production circuit, a clock signal production method, and an electronic device, relating to the technical field of communications. In the clock signal production circuit, by digital circuits such as a control word generation circuit, an initial clock generation circuit, and a spread spectrum clock generation circuit, a frequency control word is first generated on the basis of spread spectrum parameters, an initial clock signal of a target duty cycle is then generated on the basis of the frequency control word, and spread spectrum processing is finally performed on the basis of the target duty cycle of the initial clock signal and the frequency control word to obtain a spread spectrum clock signal, i.e., the entire spread spectrum process is executed by the digital circuits. Therefore, it is not necessary to control the electronic device comprising the clock signal production circuit to stop working, i.e., the normal operation of the electronic device is not affected. Moreover, according to the clock signal production circuit, real-time adjustment of spread spectrum parameters (such as spread spectrum depth) that affect a spread spectrum result can be implemented, and the spread spectrum flexibility is relatively high.

A phased locked loop includes; a load circuit that generates an output signal in response to a driving voltage, a frequency calibration circuit that generates a calibration signal in response to an output frequency of the output signal and a target frequency, and a regulator that generates the driving voltage in response to the calibration signal.

An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.

The present technology includes a replica circuit and an oscillator including the same. The replica circuit includes a first terminal to which a replica voltage having a positive voltage is supplied, a second terminal to which a ground voltage is supplied, a replica main circuit connected between the first terminal and the second terminal and configured to form a first current path in response to the replica voltage, and a replica sub circuit connected in parallel with the replica main circuit between the first terminal and the second terminal and configured to form a second current path in response to the replica voltage. A current flowing through the second current path having a replica sub current amount is less than a current flowing through the first current path having a replica main current amount.