An oscillator includes a tunable resonant circuit having an inductance and a variable capacitance coupled between first and second nodes, and a set of capacitances selectively coupleable between the first and second nodes. An input control node receiving an input control signal is coupled to the variable capacitance and set of capacitances. The tunable resonant circuit is tunable based on the input control signal. A biasing circuit biases the tunable resonant circuit to generate a variable-frequency output signal between the first and second nodes. A voltage divider generates a set of different voltage thresholds, and a set of comparator circuits with hysteresis compares the input control signal to the set of different voltage thresholds to generate a set of control signals. The capacitances in the set of capacitances are selectively coupleable between the first and second nodes as a function of control signals in the set of control signals.

A start-up phase of a phase lock loop (PLL) circuit includes supplying, by a phase comparator, of control pulses during which an output signal frequency of an oscillator increases. The increase includes an application of a pre-charge current at the oscillator input. A determination is made of a time variation of the output signal frequency. At least one adjustment is made of the intensity of the pre-charge current depending on the at least one determined time variation so as to approach a reference time variation.

A digitally controlled oscillator (DCO) that generates an output frequency clock signal without drift and can be rapidly locked to an input or reference clock is described. A variable-modulus-fixed-increment form of DCO is configured to divide the frequency of a nominally fixed frequency oscillator. A constant is derived from the ratio of a fixed increment to the desired output frequency; this constant is multiplied by the frequency of the oscillator and the modulus adjusted to keep the ratio of the input clock and the output clock constant. The frequency of the oscillator is conveniently measured by counting the number of cycles between input cycles of a reference frequency. The oscillator must be greater in frequency than the expected output and is most accurate in cases where the reference frequency is low compared to the expected output frequency.

An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to a sampling device of the SS-PLL and configured to facilitate frequency locking of the SS-PLL.

A first pulse selector outputs an output signal of a variable frequency divider to phase frequency detectors in a time division manner. A second pulse selector outputs a reference signal from a reference signal source to the phase frequency detectors in a time division manner. Outputs of the phase frequency detectors are provided, respectively, for multiple disposed charge pump circuits.

A phased locked loop (PLL) having a filter output voltage that is limited to a fraction of the voltage range accepted by the tuning port of a voltage-controlled oscillator (VCO) under control and a control system responsive to the filter output voltage and for summing the filter output voltage with an elevator voltage and applying the summed voltage to the VCO tuning port.

A frequency synthesizer circuit included in a sensor circuit of a computer system may include a voltage-controlled oscillator circuit that may generate an oscillator signal. A three-point injection technique may be used to modulate the frequency of the oscillator signal. The three-point injection includes a low-frequency component that drives a feedback divider, and two high-frequency components that drive the voltage-controlled oscillator circuit. The strengths of the three injection points are aligned using samples of a tune signal generated using results of a comparison of a referenced signal and a frequency divided version of the oscillator signal.

In an oscillator device that outputs a frequency signal based on an oscillation frequency of a crystal resonator and a frequency setting value, a frequency difference detector that obtains a difference value corresponding to a frequency difference between the output frequency of the oscillator device and an external clock signal and a temperature detector are disposed. An aging coefficient and a temperature characteristic coefficient are obtained based on a secular change of the difference value obtained in the frequency difference detector and a secular change of the detected temperature during a period where the external clock signal is obtained. Furthermore, a frequency correction value is calculated using the aging coefficient and the temperature characteristic coefficient during a holdover period, and the frequency correction value is added to the frequency setting value.

In an oscillator device that outputs a frequency signal based on an oscillation frequency of a crystal resonator and a frequency setting value, a frequency difference detector that obtains a difference value corresponding to a frequency difference between the output frequency of the oscillator device and an external clock signal and a temperature detector are disposed. An aging coefficient and a temperature characteristic coefficient are obtained based on a secular change of the difference value obtained in the frequency difference detector and a secular change of the detected temperature during a period where the external clock signal is obtained. Furthermore, a frequency correction value is calculated using the aging coefficient and the temperature characteristic coefficient during a holdover period, and the frequency correction value is added to the frequency setting value.

An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs is zero on average.