Some embodiments include apparatuses and methods of operating such apparatuses. One of the apparatuses includes a first circuit included in a phase-locked loop (PLL) to receive an input clock signal and a feedback clock signal, and to generate an output clock signal; a second circuit included in the PLL to generate the feedback clock signal from the output clock signal; and a third circuit to prevent the output clock signal from toggling during a portion of a time interval when the PLL performs an operation of aligning phases of the input clock signal and feedback clock signal.

A phase control oscillator includes a voltage control oscillator, a phase comparator, a loop filter, and a storage unit. The loop filter is configured such that if the phase control oscillator starts operating, the loop filter outputs a control voltage based on phase difference information to the voltage control oscillator. The storage unit stores deviation information indicative of a deviation between a phase difference when the loop filter outputs the control voltage in the case where the phase control oscillator starts operating and the phase difference indicated by the phase difference information. After the loop filter outputs the control voltage in response to the phase control oscillator starting operating, the loop filter outputs the control voltage based on the phase difference information output from the phase comparator and the deviation information stored in the storage unit, to the voltage control oscillator.

A clock recovery device is provided. The clock recovery device includes a clock data recovery circuit and a fast relock circuit. The clock data recovery circuit is configured to generate an output clock signal in response to an input clock signal. The clock data recovery circuit includes a charge pump for generating a control voltage and a voltage controlled block for generating the output clock signal based on the control voltage. The fast relock circuit is configured to convert a comparison signal indicating a comparison result between the input clock signal and the output clock signal to an analog output voltage. When the charge pump is disabled, an output path of the fast relock circuit is turned on, and the analog output voltage is applied to an input of the voltage controlled block.

A local oscillator generator (LO generator) may be configured to transmit an LO signal to a mixer. The LO generator may include an input buffer configured to generate a first internal oscillator signal based on the input oscillator signal. The LO generator may include a frequency dividing circuit configured to generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal. The LO generator may include an output buffer configured to generate the LO signal based on the second internal oscillator signal. The input buffer and the frequency dividing circuit may each be configured to receive a power voltage independently of the output buffer.

A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal. The circuit further includes a digital-to-analog conversion unit that includes a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal. The circuit includes circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator. The pre-processing stage includes a word-length adaption unit configured to reduce the word-lengths of the digital words and a sigma-delta modulator coupled to the word-length adaption unit downstream thereof and configured to modulate the sequence of digital words having reduced word-lengths.

A system and method for correcting for phase errors, in a phase locked loop, resulting from spread spectrum clocking involving a reference clock signal having a frequency modulation. A correction generation circuit generates an offset signal, that when injected after the charge pump of the phase locked loop, causes the voltage controlled oscillator to produce a signal with substantially the same frequency modulation, thereby reducing the phase error. The correction generation circuit may include a timing estimation circuit for estimating the times at which transitions (between positive-sloping and negative-sloping portions of the triangle wave) occur, and an amplitude estimation circuit for estimating the amplitude of the offset signal that results in a reduction in the phase error.

The present disclosure relates to a method for demodulating a modulated signal and a receiver. The receiver comprises: a phase detector with a first and second input, the first input being adapted to receive a modulated input signal; a comparator comprising an input coupled to an output of the phase detector; a frequency-offset cancellation block comprising an input coupled to an output of the comparator. The receiver includes a digitally controlled oscillator comprising: a control input coupled to an output of the comparator and an output of the frequency-offset cancellation block; and an output coupled to the second input of the phase detector.

A flash analog-to-digital converter (ADC) receives an input control signal and performs coarse tuning of a frequency of an output signal, produced between first and second nodes having an inductance coupled therebetween. The flash ADC quantizes an operating frequency range for the output signal produced between the first and second nodes as M.Math.f, where M is an integer from 0 to N1, where N is a number of intervals into which a frequency range for the output signal is divided, and where f is a resulting frequency step produced by the quantizing. The value of M is generated based upon the input control signal and a word controlling switches of a plurality of switched capacitance circuits associated with the first and second nodes to close ones of those switches associated with the control word to coarsely tune the frequency of the output signal.

Certain aspects of the present disclosure are directed towards apparatus and techniques for receiver calibration. An example apparatus generally includes: a first receiver having a first oscillating signal generation circuit, an output of the first oscillating signal generation circuit being coupled to an input of a first splitter, wherein the first splitter has multiple outputs; a second receiver having a second oscillating signal generation circuit coupled to an LO input of each of a first plurality of mixers of the second receiver; and signal paths between the multiple outputs of the first splitter and signal inputs of the first plurality of mixers, respectively.

A method of generating an output signal includes determining a sampling period N according to a number of most significant bits (MSBs) of a divider number control signal. The method also includes determining a first logic value of a control signal by a comparing circuit based on the sampling period N, and generating a coarse tuning signal by a code generating circuit based on a phase difference signal and the control signal. When an M-th least significant bit (LSB) of the number of MSBs of the divider number control signal equals a second logic value, the sampling period N is set based on the M-th LSB of the number of MSBs of the divider number control signal.