A distance-measuring imaging device includes: a timing controller that outputs one or more timing signals; a light receiver that receives reflected light that is light emitted by a light source and reflected by a subject; a phase adjustment circuit that outputs at least one signal out of a light emission control signal and an exposure control signal, based on the one or more timing signals, the light emission control signal being used for causing the light source to emit light to the subject, the exposure control signal being used for causing the light receiver to start exposure. The phase adjustment circuit includes one or more DLL circuits each of which determines, for at least one of the one or more timing signals, at least one of a phase of a rising edge or a phase of a falling edge of the at least one signal.

An all-digital phase locked loop (ADPLL) is provided. The ADPLL comprises a pattern generator adapted to generate a frequency control word (FCW) based on a predefined setting and a system clock. In addition, the ADPLL comprises a phase accumulator adapted to translate the FCW into a phase trajectory. The ADPLL further comprises a phase comparator adapted to generate a phase error signal representing a difference between the phase trajectory and the phase of an output oscillation frequency. Moreover, the ADPLL comprises a controller adapted to control a phase of the output oscillation frequency with respect to the phase trajectory.

In one embodiment, a phase lock loop circuit includes a control circuit, wherein the control circuit is configured to input an estimation having a second frequency and a second phase. The second frequency is selected from a range of frequencies including a first frequency from an acquired signal. A numerically controlled oscillator is coupled to the control circuit, wherein the control circuit is configured to control an output response of the numerically controlled oscillator. The numerically controlled oscillator is configured to receive the estimation from the control circuit and generate an output signal in response to the estimation. A phase detector is coupled to the control circuit and the numerically controlled oscillator, wherein the phase detector is configured to compare the first signal and the output signal and produce a comparison output, the comparison output indicative of a phase difference between the first signal and the estimation.

An equalizer control device includes a first circuit configured to, upon receipt of a data signal that has been equalized by a continuous time linear equalizer (CTLE) circuit, output a first signal related to a first number of times a waveform of the data signal crosses a threshold value or differential signals of the data signal cross each other. A second circuit is configured to count the first number during a particular time period based on the output first signal, and select one of equalization parameters to be set to the CTLE circuit based on the counted first number.

Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

A circuit for correcting phase interpolator rollover integral non-linearity errors includes a rollover detector circuit for detecting when an interpolator rollover event of a phase integer portion of a phase interpolator has occurred, and a correction circuit that adds a signed predistortion correction to the VCO clock cycle fraction value of the phase interpolator when the rollover detector circuit has detected the interpolator rollover event.

In an oscillator device that outputs a frequency signal based on an oscillation frequency of a crystal resonator and a frequency setting value, a frequency difference detector that obtains a difference value corresponding to a frequency difference between the output frequency of the oscillator device and an external clock signal and a temperature detector are disposed. An aging coefficient and a temperature characteristic coefficient are obtained based on a secular change of the difference value obtained in the frequency difference detector and a secular change of the detected temperature during a period where the external clock signal is obtained. Furthermore, a frequency correction value is calculated using the aging coefficient and the temperature characteristic coefficient during a holdover period, and the frequency correction value is added to the frequency setting value.

A method for initializing a phase adder circuit including a multiplier circuit with its two inputs receiving signals of frequency f.sub.o, a mixer circuit, an amplifier circuit, a low pass loop filter, and a voltage controlled oscillator (VCO), the method including: during a first phase, determining a reference voltage which when applied to the VCO causes it to produce a signal having a frequency of nf.sub.0; during a second phase, supplying a signal of frequency nf.sub.o to a first input of the mixer and a signal of frequency (nf.sub.o+Δf) to a second input of the mixer; and determining an adjustment signal which when applied to the amplifier circuit causes the amplifier circuit to output a signal having a DC component equal to the reference voltage; and during a third phase, forming a primary phase locked loop (PLL) circuit including the mixer, the amplifier circuit, the low pass loop filter and the VCO; and applying the adjustment signal to the amplifier circuit.

A delay lock loop and a phase locking method thereof are provided. The delay lock loop includes a first divider, a delay line, a frequency multiplier, a second divider, a phase detection and controlling circuit and a setting signal generator. The first divider generates a divided reference clock signal. The second divider generates a first feedback clock signal and a second feedback clock signal which are complementary by dividing an output clock signal, and generates a selected feedback clock signal by selecting the first or second feedback clock signal according to a setting signal. The phase detection and controlling circuit compares phases of the selected feedback clock signal and the divided reference clock signal to generate a delay control signal. The setting signal generator samples the divided reference clock signal by the first feedback clock signal to generate the setting signal.

Locking time for a phase-locked loop is decreased by selectively controlling a division value of the feedback divider during the first division cycle to reduce the initial phase error. The division value of the feedback divider during the first division cycle is selectively set such that the locking phase relationship between the two phase detector input signals is achieved at the end of the first division cycle.