Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.

An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions, a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal, and a position controller suitable for varying the first and second target positions according to an operation mode.

A system includes memory and at least one processor coupled to the memory and configured to receive a phase detector (PD) error signal. The PD error signal indicates a leading clock signal of at least two clock signals. The at least two clock signals are generated based on an input clock signal and a voltage control signal. The at least one processor receives a toggling signal indicating whether one of the at least two clock signals is toggling between clock cycles of the input clock signal. A code value is generated based on the PD error signal and the toggling signal. The at least one processor causes generation of the voltage control signal based on the code value.

Phase lock loop calibration methods can be accelerated, and the accelerated method incorporated in integrated circuits and systems. One illustrative calibration method for use in a controller determines a calibrated value of a calibration parameter for a phase lock loop configured to generate a clock signal. The method includes: finding a lower bound by stepping downward from an initial value of the calibration parameter while a frequency error remains below a predetermined threshold; finding an upper bound by stepping upward from the initial value while the frequency error remains below the predetermined threshold; and using a value greater than or equal to the lower bound and less than or equal to the upper bound as the calibrated value.

Phase lock loop calibration methods can be accelerated, and the accelerated method incorporated in integrated circuits and systems. One illustrative calibration method for use in a controller determines a calibrated value of a calibration parameter for a phase lock loop configured to generate a clock signal. The method includes: finding a lower bound by stepping downward from an initial value of the calibration parameter while a frequency error remains below a predetermined threshold; finding an upper bound by stepping upward from the initial value while the frequency error remains below the predetermined threshold; and using a value greater than or equal to the lower bound and less than or equal to the upper bound as the calibrated value.