A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

Provided is frequency-modulated continuous wave generator. The frequency-modulated continuous wave generator includes a ramp signal generator configured to generate an analog ramp signal, a reference signal generator configured to generate a reference signal based on the analog ramp signal, a phase locked loop configured to output a control voltage based on the reference signal, and a voltage-controlled oscillator configured to generate a frequency-modulated continuous wave based on the control voltage. The ramp signal generator is further configured to generate the analog ramp signal based on a feedback signal based on the frequency-modulated continuous wave.

Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.

A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

An all digital phase locked loop system for tracking a variable frequency input signal and method of operation are described. The ADPLL system includes a digital phase locked loop, including a digitally controlled oscillator, and a model of the digitally controller oscillator. The model represents the behaviour of the digitally controlled oscillator as a function of frequency and has a model input arranged to receive a signal indicating a current target frequency. The model is configured to output at least one control signal to control the frequency of the digitally controlled oscillator to be closer to the current target frequency. The digital phase locked loop is configured to control the digitally controlled oscillator to reduce any difference between the frequency of the digitally controlled oscillator and the current target frequency arising from any deviation of the model of the digitally controlled oscillator from the digitally controlled oscillator.

An automatic calibration of a clock of a wireless portable part with respect to a clock of a fixed part in a field environment. The calibration performed in the field environment negates the need to calibrate the clock during manufacture and negates the need for an initial field recalibration because of temperature differences between manufacture and the field. In performing the calibration the frequency of the clock of the portable part is varied until the portable part is synchronous with the fixed part to with in a range of timing bits. The portable part is declared calibrated after remaining calibrated for a defined number of data frames.

An automatic calibration of a clock of a wireless portable part with respect to a clock of a fixed part in a field environment. The calibration performed in the field environment negates the need to calibrate the clock during manufacture and negates the need for an initial field recalibration because of temperature differences between manufacture and the field. In performing the calibration the frequency of the clock of the portable part is varied until the portable part is synchronous with the fixed part to with in a range of timing bits. The portable part is declared calibrated after remaining calibrated for a defined number of data frames.

A method of calibrating a digitally controlled oscillator (DCO). The method comprises configuring a fine tuning capacitive component of the DCO into a minimum capacitance configuration therefor, configuring a coarse tuning capacitive component of the DCO into a first configuration therefor and determining a resulting first output frequency of the DCO. The method further comprises configuring the coarse tuning capacitive component into a second configuration therefor, the second and first configurations of the coarse tuning capacitive component being capacitively increasing consecutive configurations respectively, configuring the fine tuning capacitive component into a maximum capacitance configuration therefor, determining control signal settings for a resolution adjustment component of the DCO that achieve a resulting output frequency of the DCO equal to the determined first output frequency, and generating calibration data for the second configuration of the coarse tuning capacitive component comprising the determined control signal settings for the resolution adjustment component.

An apparatus and method are provided to re-configure an existing low-jitter phase locked loop (PLL) circuit for fast start-up during system wake-up. During system start-up, a feed-back path of the PLL is disconnected to independently control the VCO frequency. This independently controlled VCO then injects energy into a resonator (e.g., a crustal oscillator) for its fast start-up. Once a resonance frequency of the resonator is detected and an oscillation builds up in the resonator, a VCO control voltage is stored. The PLL feedback is then restored and the stored VCO control voltage is applied to perform phase-locking operation. Since the PLL control voltage is already set to the desired operating point, the PLL lock time is very small.

The disclosure provides a radar apparatus. The radar apparatus includes a transmit unit that generates a first signal in response to a reference clock and a feedback clock. The first signal is scattered by one or more obstacles to generate a second signal. A receive unit receives the second signal and generates N samples corresponding to the second signal. N is an integer. A conditioning circuit is coupled to the transmit unit and the receive unit. The conditioning circuit receives the N samples corresponding to the second signal, and generates N new samples using an error between the feedback clock and the reference clock.