Various embodiments relate to a network node and method thereof including a high stability oscillator and a holdover phase-locked loop (PLL) wherein the holdover PLL is configured to perform a holdover function by receiving a system clock signal, disciplining the high stability oscillator using the system clock signal to generate a local reference signal, and providing the local reference signal as the system clock signal when the system clock signal becomes unavailable.

The present application provides a clock switching method, a clock switching apparatus, an electronic device, and a readable storage medium, the clock switching method includes: in a case where a first reference clock is determined to be in a locked state, determining an average control word according to a preset duration and an obtained real frequency tuning word; in a case where the first reference clock is determined to be in an invalid state, determining a compensation phase difference by using the average control word as a frequency control word of a digital phase locked loop; performing a phase compensation on a second reference clock according to the compensation phase difference to obtain an updated second reference clock; and switching the first reference clock to the updated second reference clock.

Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

Various embodiments relate to a network node and method thereof including a high stability oscillator and a holdover phase-locked loop (PLL) wherein the holdover PLL is configured to perform a holdover function by receiving a system clock signal, disciplining the high stability oscillator using the system clock signal to generate a local reference signal, and providing the local reference signal as the system clock signal when the system clock signal becomes unavailable.

In a reference signal generator including a synchronization circuit configured to convert a digital signal into an analog signal, supply this signal to a voltage controlled oscillator, and control the voltage controlled oscillator to obtain a signal synchronized with the reference signal, without an accumulation of quantization error in a holdover control in which an acquisition of a reference signal is not available. The reference signal generator includes a phase synchronization circuit and a controller. The phase synchronization circuit controls the reference signal outputted from the oscillator, according to a control signal obtained based on the reference signal. The controller generates a free-running control signal and controls the oscillator when the reference signal becomes unavailable. The oscillator receives discrete values and oscillates accordingly. A digital delta-sigma modulator configured to modulate the free-running control signal of the controller is disposed in a subsequent stage of the controller.

An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wireless device. Each transceiver may include a configurable clock divider to divide the distributed LO clock signal and generate an output clock signal. A phase detector compares output clock signals from each of the configurable clock dividers and generates an output signal in accordance with a determined phase difference. The phase detector output signal may cause at least one of the configurable clock dividers to modify its respective output clock signal, and thereby synchronize output clock signals between different configurable clock dividers. In some embodiments, a clock signal from a configurable clock divider may be modified (shifted) by approximately 90 or 180 degrees.

A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.

Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal. When the control circuit determines that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch. After the selected reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock.

Disclosed is a circuit, such as a clock conditioner, that provides an improved ability to exit from holdover operations, most notably during conditions where the clock signal inputs to a PLL of the clock conditioner are significantly out of phase. The circuit utilizes the PLL to generate output clocks based on a reference clock and a feedback clock. During holdover mode, the PLL is unlocked. When the reference clock becomes available and holdover mode can be exited, a holdover controller issues a reset signal that triggers a synchronization of the phases of the inputs to the PLL. The reset signal causes the feedback divider component that generates the feedback clock input to reset its phase and adjust its divide ratio for at least the first divide cycle after restart so that its next rising edge will be phase-aligned with the reference clock. Once the two inputs of the PLL phase detector are phase-aligned, the PLL is re-enabled and the PLL smoothly resumes normal operation.

A wireless communication apparatus has an analog control loop circuitry to generate an analog control signal which adjusts a phase of a voltage-controlled oscillation signal, an integrator to integrate the analog control signal, a phase adjuster to adjust a phase of the voltage-controlled oscillation signal, a digital control loop circuitry, in a first mode, to match a frequency of the voltage-controlled oscillation signal to a frequency of the received signal based on an output signal of the phase adjuster, and in a second mode, to generate a digital control signal which is opposite in phase to the analog control signal and has a frequency, a voltage-controlled oscillator to generate the voltage-controlled oscillation signal based on the analog and digital control signals, and a signal switch to supply the analog control signal to the integrator in the first mode and to the voltage-controlled oscillator in the second mode.