A frequency converter control unit has: a serial control unit interface, a control unit clock pulse generator for generating a control unit clock pulse, and a control unit processor which is designed to define a control parameter depending on an actual value. A power unit has a data connection to the control unit and has several power semiconductors, a power unit clock pulse generator for generating an adjustable power unit clock pulse, a serial power unit interface, a clock pulse generator adjustment unit which has a signal connection to the power unit interface and which adjusts the power unit clock pulse depending on signals received by the power unit on the power unit interface, a power unit processor which controls the power semiconductors depending on the control parameter and the power unit clock pulse, and a sensor unit that determines the actual value. The control unit transmits the control parameter via the control unit interface to the power unit. The power unit transmits the actual value via the power unit interface to the control unit.

The present invention continuously generates a signal at an acceptable frequency without utilizing the PLL to modify the operation of the VCO. When the VCO is initialized properly to output a signal at a specific frequency, the VCO operates on its own to continuously output signals, and the VCO state is modified at regular intervals. Thus, when the interval is short enough and when the VCO is modified to the initial state every time, the VCO state will not deviate significantly from the initial state during these intervals. Thus, the VCO continuously generate signals with frequencies acceptably closed to the specific frequency. That is to say, the invention utilizes the injection lock to modify the operation of the VCO. To compare with the convention skills utilizing the PLL which has to feed back the signal generated by the VCO to the PLL for modifying the VCO state dynamically, the utilization of the injection lock simplifies the hardware and streamlines the process. Thus, the invention is an alternation to the convention technologies with lower cost and similar accuracy.

To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.

Apparatus for clock synchronization comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.

Disclosed is a pulse elimination circuit, a voltage detection circuit and a detection method, referring to a field of electronic circuit technology. The pulse elimination circuit comprises: a clock generation circuit configured to receive a logic signal and a first input signal and generate a clock signal according to the logic signal and the first input signal; a counter coupled with the clock generation circuit and configured to receive the clock signal and count a number of cycles of the clock signal to generate a second input signal; a signal output circuit coupled to the counter and configured to supply a first input signal to the clock generation circuit and generate a pulse elimination signal based on the second input signal. Therefore, in a process of voltage detection, this circuit can eliminate a false trigger caused by short pulse and improve voltage detection accuracy.