The variation of the oscillation frequency of an oscillator can be suppressed even in the case where the amount of interference with the oscillator accompanied by an amplifying operation of a power amplifier and the polarity are not constant. An oscillator is configured to be capable of oscillating at an oscillation frequency in accordance with control signals Vcont and FREQ_CTRL. A phase locked loop allows the oscillator to output an oscillation signal Vout in synchronization with a reference signal RELCLK using the control signal Vcont. A power amplifier amplifies the electric power of the oscillation signal Vout. A variation detection unit detects a variation with respect to the time change of the control signal Vcont after an amplifying operation is started by the power amplifier causing 3interference with the oscillator. A variation correction unit generates the control signal FREQ_CTRL on the basis of the variation detected by the variation detection unit, and corrects the variation of the oscillation frequency caused by the interference accompanied by the amplifying operation of the power amplifier.

A clock scheme circuit with low power consumption is shown. A local clock generator is coupled to a global clock generator through a global clock trace to receive a global clock signal, and generate a local clock signal based on the global clock signal. The local clock generator uses a frequency multiplier to multiply the frequency of the global clock signal by a multiplication factor of not less than 1. Thus, the global clock signal transferred through the global clock trace can be a lower-frequency signal in comparison with the local clock signal. The power consumption along the global clock trace is considerably reduced.

Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number N.sub.K cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.

A waveform generator circuit provides low spurious output signal and includes a primary DDS for generating a RF signal at a first frequency. A DAC receives an output signal from the primary DDS and converts the digital DDS output to an analog output. A spectrum analyzer identifies spurious signals in the DAC output determining the amplitude and frequency characteristics of the spurious signals. The waveform generator includes at least one cancellation DDS configured to generate a pre-distortion signal corresponding to frequencies where spurious signals are expected due to non-linearities in the DAC circuitry. The pre-distortion signals are phase offset from the determined spurious signals to cancel the spurious signals. The pre-distortion signals are combined with the output of the primary DDS. The combined signal contains the primary DDS output signal and pre-distortion signals to produce an analog output signal which cancels out the expected spurious signals.

Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number N.sub.K cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.

In various embodiments, a frequency dividing circuit is provided. The frequency dividing circuit may include a first circuit including an m-bit multiplexer configured to receive a positive binary word and a negative binary word as inputs. The frequency dividing circuit may receive a controlled oscillator output signal and a complement of the controlled oscillator output signal, generate a frequency dividing circuit output signal from the controlled oscillator output signal and the complement of the controlled oscillator output signal using the positive binary word and the negative binary word. A ratio of the frequency dividing circuit output signal frequency to the controlled oscillator output signal frequency is a decimal value greater than zero and less than one and is determined using a ratio of a value of the positive binary word to a sum of the value of the positive binary word and an absolute value of the negative binary word.

A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.

A method and device for generating a multi-rate clock signal using a ring voltage-controlled oscillator based phase-locked loop is provided. The device includes a delay line having a length extending beyond a predetermined length required for operation of the phase-locked loop. The device further includes a tap tuning logic circuit coupled to the delay line. The delay line receives an input signal and a tuning voltage from the phase frequency detector, charge pump and loop filter circuits and generates a plurality of tapped output signals. The plurality of tapped output signals is received by the integrated digital multi-rate clock generator configured to create a plurality of clock signals.

In various embodiments, a frequency dividing circuit is provided. The frequency dividing circuit may include a first circuit including an m-bit multiplexer configured to receive a positive binary word and a negative binary word as inputs. The frequency dividing circuit may receive a controlled oscillator output signal and a complement of the controlled oscillator output signal, generate a frequency dividing circuit output signal from the controlled oscillator output signal and the complement of the controlled oscillator output signal using the positive binary word and the negative binary word. A ratio of the frequency dividing circuit output signal frequency to the controlled oscillator output signal frequency is a decimal value greater than zero and less than one and is determined using a ratio of a value of the positive binary word to a sum of the value of the positive binary word and an absolute value of the negative binary word.

In various embodiments, a frequency dividing circuit is provided. The frequency dividing circuit may include a first circuit including an m-bit multiplexer configured to receive a positive binary word and a negative binary word as inputs. The frequency dividing circuit may receive a controlled oscillator output signal and a complement of the controlled oscillator output signal, generate a frequency dividing circuit output signal from the controlled oscillator output signal and the complement of the controlled oscillator output signal using the positive binary word and the negative binary word. A ratio of the frequency dividing circuit output signal frequency to the controlled oscillator output signal frequency is a decimal value greater than zero and less than one and is determined using a ratio of a value of the positive binary word to a sum of the value of the positive binary word and an absolute value of the negative binary word.