A voltage controlled oscillator (VCO) in a frequency synthesizer generates an output signal having a target frequency by being coarse tuned in accordance with a channel code derived through a binary tree search. Thereafter, the output signal of the VCO may be further tuned using a phase lock loop (PLL) circuit. Each stage of the binary tree search includes a comparison step that determines a channel code bit, and another step that confirms that the channel code converges to a final channel code within an established stage range value.

A start-up phase of a phase lock loop (PLL) circuit includes supplying, by a phase comparator, of control pulses during which an output signal frequency of an oscillator increases. The increase includes an application of a pre-charge current at the oscillator input. A determination is made of a time variation of the output signal frequency. At least one adjustment is made of the intensity of the pre-charge current depending on the at least one determined time variation so as to approach a reference time variation.

An oscillator calibration circuit is presented. The oscillator calibration includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session; and a second FLC coupled to a second oscillator, wherein the second FLC calibrates the frequency of the second oscillator using the over-the-air reference signal, wherein the second FLC calibrates the second oscillator immediately prior to a data transmission session and remains free running during the data transmission session.

An oscillator calibration circuit is presented. The oscillator calibration includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session; and a second FLC coupled to a second oscillator, wherein the second FLC calibrates the frequency of the second oscillator using the over-the-air reference signal, wherein the second FLC calibrates the second oscillator immediately prior to a data transmission session and remains free running during the data transmission session.

An auto trimming device includes an oscillator configured to generate an oscillator clock signal, a subtractor configured to receive an expected value for a target frequency and the oscillator clock signal, configured to output a difference value between the expected value and the oscillator clock signal, an index value selector configured to calculate a unit index value using the difference value and configured to detect and output a target index value from the unit index value, an index value register configured to output an oscillator trimming code corresponding to the target index value to the oscillator, and an embedded memory configured to store the oscillator trimming code as a target oscillator trimming code for the target frequency.

An auto trimming device includes an oscillator configured to generate an oscillator clock signal, a subtractor configured to receive an expected value for a target frequency and the oscillator clock signal, configured to output a difference value between the expected value and the oscillator clock signal, an index value selector configured to calculate a unit index value using the difference value and configured to detect and output a target index value from the unit index value, an index value register configured to output an oscillator trimming code corresponding to the target index value to the oscillator, and an embedded memory configured to store the oscillator trimming code as a target oscillator trimming code for the target frequency.

Oscillator circuitry is disclosed. The oscillator circuitry comprises a free-running oscillator for generating pulses at a frequency, and a frequency adjustment circuit for adaptively adjusting the frequency of the free-running oscillator. The frequency adjustment circuit comprises a counter configured to count a number of pulses generated by the free-running oscillator and logic configured to compare the number of pulses with an expected number of pulses (corresponding to a target frequency) to determine a difference value and to adjust the frequency of the free-running oscillator in dependence on the difference value. The frequency adjustment circuit is configured, in response to receiving a synchronisation pulse, to trigger an update of the number of pulses to be compared.

Oscillator circuitry is disclosed. The oscillator circuitry comprises a free-running oscillator for generating pulses at a frequency, and a frequency adjustment circuit for adaptively adjusting the frequency of the free-running oscillator. The frequency adjustment circuit comprises a counter configured to count a number of pulses generated by the free-running oscillator and logic configured to compare the number of pulses with an expected number of pulses (corresponding to a target frequency) to determine a difference value and to adjust the frequency of the free-running oscillator in dependence on the difference value. The frequency adjustment circuit is configured, in response to receiving a synchronisation pulse, to trigger an update of the number of pulses to be compared.

A high-density logic circuit device low-frequency phase-locked loop system includes a digital logic input-output module; an internal clock; an instant-lock module; an instant-adjust error module; a high-speed count comparator; a multiplication factor-is-zero-state detect module with a reset function; a pulse generator; and a high-speed pulse generator. The high-speed count comparator includes a high-speed counter and a high-speed comparator. The input-output module receives an input frequency and transmits an output frequency. The instant lock module locks the output frequency in phase to a leading edge the input frequency within two internal propagation delays. The instant-adjust error module emits a pulse request until a last pulse is identified. The high-speed count comparator receives the pulse request and emits the output frequency. The pulse generators receive the input frequency and internal clock pulses and output a frequency-in pulse. The HDL device has a digital low-frequency PLL function without the use of external components.

A high-density logic circuit device low-frequency phase-locked loop system includes a digital logic input-output module; an internal clock; an instant-lock module; an instant-adjust error module; a high-speed count comparator; a multiplication factor-is-zero-state detect module with a reset function; a pulse generator; and a high-speed pulse generator. The high-speed count comparator includes a high-speed counter and a high-speed comparator. The input-output module receives an input frequency and transmits an output frequency. The instant lock module locks the output frequency in phase to a leading edge the input frequency within two internal propagation delays. The instant-adjust error module emits a pulse request until a last pulse is identified. The high-speed count comparator receives the pulse request and emits the output frequency. The pulse generators receive the input frequency and internal clock pulses and output a frequency-in pulse. The HDL device has a digital low-frequency PLL function without the use of external components.