An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal.

An oscillator includes: an outer package; an inner package accommodated in the outer package and fixed to the outer package via a heat insulating member; a vibration element accommodated in the inner package; a temperature sensor; a first circuit element accommodated in the inner package and including an oscillation circuit configured to oscillate the vibration element and generate a temperature-compensated oscillation signal based on the temperature sensor; and a second circuit element fixed to the outer package and including a frequency control circuit configured to control a frequency of the oscillation signal.

A wireless system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock. The LO signal generation circuit includes an active oscillator. The active oscillator generates the reference clock, wherein the active oscillator includes at least one active component, and does not include an electromechanical resonator. The RX circuit generates a down-converted RX signal by performing down-conversion upon an RX input signal according to the LO signal. The calibration circuit generates a frequency calibration control output according to a signal characteristic of the down-converted RX signal, and outputs the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.

A wireless system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock. The LO signal generation circuit includes an active oscillator. The active oscillator generates the reference clock, wherein the active oscillator includes at least one active component, and does not include an electromechanical resonator. The RX circuit generates a down-converted RX signal by performing down-conversion upon an RX input signal according to the LO signal. The calibration circuit generates a frequency calibration control output according to a signal characteristic of the down-converted RX signal, and outputs the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.

A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.

A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.

A frequency synthesizing device includes a voltage-controlled oscillator receiving an adjusting signal and generating an output signal according to the adjusting signal. A feedback frequency divider having a plurality of divisor values receives the output signal and generates a feedback signal after performing frequency dividing. An automatic frequency calibration circuit of the frequency synthesizing device includes a first frequency divider receiving a reference frequency, and a second frequency divider receiving the feedback signal. A comparator of the automatic frequency calibration circuit receives and compares outputs from the first frequency divider and the second frequency divider in a predetermined period to generate a comparing result. A state machine outputs the adjusting signal according to the comparing result in a calibration mode.

A system includes a digital phase-locked loop (DPLL) having a loop filter and a digitally-controlled oscillator (DCO). The system also includes a clock generator coupled to an output of the DPLL, and a plurality of clock domains coupled to the clock generator. The DPLL is configured to transition between a low power mode and a normal mode, wherein the loop filter is configured to maintain its value when the DPLL transitions from the normal mode to the low power mode. The DCO is configured to output a DCO clock signal based on the maintained loop filter value when the DPLL transitions from the low power mode to the normal mode.

A delay measurement circuit includes a first skew circuit disposed proximate to a first bonding pad configured to receive a first clock signal having a first frequency. The delay measurement circuit includes a second skew circuit disposed proximate to a second bonding pad configured to receive a second clock signal having a second frequency. The first and second skew circuits each have a first mode of operation as zero-delay-return path and a second mode of operation as a synchronized pass path. The delay measurement circuit includes a pair of conductive traces coupled to the first skew circuit, another pair of conductive traces coupled to the second skew circuit, a time-to-digital converter circuit, and a switch circuit configured to selectively couple the time-to-digital converter circuit to the first skew circuit via the pair of conductive traces and the second skew circuit via the other pair of conductive traces.

A frequency divider circuit includes a counter configured to generate a counter signal responsive to a frequency of a clock signal and a frequency ratio, and a compensation circuit coupled to the counter, and configured to generate an output signal. The output signal has a frequency equal to the frequency of the clock signal divided by a frequency ratio, and a duty cycle lower than 50% and greater than 1/r, where r is the frequency ratio.