An automatic frequency calibration and lock detection circuit includes a frequency error generator circuit, an automatic frequency calibration signal generator circuit, and a lock flag generator circuit. The frequency error generator circuit generates a frequency error signal based on a reference frequency signal and an output frequency signal. The frequency error signal represents a difference between a frequency of the output frequency signal and a target frequency. The automatic frequency calibration signal generator circuit generates an automatic frequency calibration output signal and an automatic frequency calibration done signal based on the frequency error signal and a first clock signal. The lock flag generator circuit generates a lock done signal based on the frequency error signal, the automatic frequency calibration done signal and a second clock signal. The frequency error generator circuit is shared by the automatic frequency calibration signal generator circuit and the lock flag generator circuit.

A digitally controlled oscillator (100), a synthesizer module (200), a synthesizer (300), and a method for producing an electrical audio signal are presented. The oscillator (100) comprises a digital processing unit (10) configured to generate a first pulse wave at a first output (PulseUp) of the processing unit (10), wherein the first pulse wave is arranged to include pulses at at least two different frequencies. The oscillator (100) further comprises a summing circuit (30) and a linear wave shaper (20). The output (PulseUp) of the processing unit (10) is connected to the summing circuit (30) which is arranged to produce a resultant signal based on at least the first pulse wave. The resultant signal is arranged to be fed into the linear wave shaper (20) which is arranged to produce an output signal at the output (OUT) of the oscillator (100) based on modifying the resultant signal.

A digitally controlled oscillator (100), a synthesizer module (200), a synthesizer (300), and a method for producing an electrical audio signal are presented. The oscillator (100) comprises a digital processing unit (10) configured to generate a first pulse wave at a first output (PulseUp) of the processing unit (10), wherein the first pulse wave is arranged to include pulses at at least two different frequencies. The oscillator (100) further comprises a summing circuit (30) and a linear wave shaper (20). The output (PulseUp) of the processing unit (10) is connected to the summing circuit (30) which is arranged to produce a resultant signal based on at least the first pulse wave. The resultant signal is arranged to be fed into the linear wave shaper (20) which is arranged to produce an output signal at the output (OUT) of the oscillator (100) based on modifying the resultant signal.

Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (F.sub.S)(F.sub.S/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential F.sub.S/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.

Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.

A technology related to an electronic circuit, specifically, a phase locked loop or a frequency synthesizing apparatus, is disclosed. The frequency synthesizing apparatus includes an injection locked frequency divider and a replica frequency divider having the same circuit configuration as the injection locked frequency divider. A control value required for self-oscillating at a target frequency using the replica frequency divider is determined. When the injection locked frequency divider fails injection locking on a first attempt, the injection locking may be attempted using the determined control value. On the first attempt, the control value of the injection locked frequency divider may be determined and stored in advance according to a temperature and a supply voltage.

A delay measurement circuit includes a first skew circuit disposed proximate to a first bonding pad configured to receive a first clock signal having a first frequency. The delay measurement circuit includes a second skew circuit disposed proximate to a second bonding pad configured to receive a second clock signal having a second frequency. The first and second skew circuits each have a first mode of operation as zero-delay-return path and a second mode of operation as a synchronized pass path. The delay measurement circuit includes a pair of conductive traces coupled to the first skew circuit, another pair of conductive traces coupled to the second skew circuit, a time-to-digital converter circuit, and a switch circuit configured to selectively couple the time-to-digital converter circuit to the first skew circuit via the pair of conductive traces and the second skew circuit via the other pair of conductive traces.

A clock device includes a first phase interpolator circuit, a detector circuit, and a digital controller circuitry. The first phase interpolator circuit generates a second reference clock signal according to a first control signal and at least one first reference clock signal. The detector circuit generates an error signal according to a difference between a receiver signal and the second reference clock signal, in which the receiver signal is a receiver clock signal from a receiver circuit or an input signal that has been equalized by the receiver circuit. The digital controller circuitry generates the first control signal and a second control signal according to the error signal, and updates the second control signal according to a change of the first control signal, in which the second control signal is for generating a transmitter clock signal of a transmitter circuit.

A semiconductor device includes a clock generating circuit and a jitter measurement circuit. The clock generating circuit is input with a control value for changing a cycle of the clock thereof. The jitter measurement circuit has a first logic circuit operated with using an output clock of the clock generating circuit as an input and a first delay element, and is configured to output the presence/absence of a jitter of the clock generating circuit.

In some examples, a device comprises a first driver coupled to a first node, the first node to couple to a first load external to the device. The device comprises a second driver coupled to a second node, the second node coupled to a second load internal to the device. The device comprises a comparison circuit having an inverting input coupled to the first node and a non-inverting input coupled to the second node. Sizes of the second driver and the second load are configured proportionately to sizes of the first driver and the first load, respectively.