A semiconductor device according to the present embodiment includes a plurality of switching elements and a plurality of variable capacitance elements. The switching elements are switching elements connected in series between a first control terminal and a second control terminal and plural types of capacitance control signals can be supplied to the first control terminal and the second control terminal. The variable capacitance elements have capacitance control terminals connected to corresponding one ends of the switching elements, respectively.

A phase locked loop includes a phase detector outputting a first signal corresponding to a phase difference of a reference frequency signal and a division frequency signal, a charge pump amplifying a first signal to output a second signal, a loop filter filtering the second signal to output a third signal, a voltage-to-current converter receiving the third signal and outputting a fourth signal, a digital-to-analog converter outputting a fifth signal based on the fourth signal and a digital compensation signal, an oscillator outputting an output frequency signal having a frequency corresponding to the fifth signal, a divider dividing the frequency of the output frequency signal to output the division frequency signal and a compensation frequency signal, and an automatic frequency calibrator compensating for the voltage-to-current converter based on a difference between a frequency of the compensation frequency signal and a frequency of a reference frequency signal.

In an embodiment, an electronic device may include a first frequency synthesizing circuit outputting a second electronic signal from a first electronic signal, a second frequency synthesizing circuit outputting a fourth electronic signal for converting a frequency of a third electronic signal obtained from the first electronic signal based on the second electronic signal, and a communication processor. The communication processor may be configured to transmit, to the first frequency synthesizing circuit, a first parameter indicating a frequency of the second electronic signal, and changing based on a first preset frequency interval according to a first preset period. The communication processor may be configured to transmit, to the second frequency synthesizing circuit, a second parameter indicating a frequency of the fourth electronic signal based on a frequency of a second clock signal, and changing based on a second preset frequency interval different from the first preset frequency interval.

A phase-locked loop (PLL) is implemented to have another (second) PLL in place of the controlled oscillator. When a known frequency change in the frequency of the output clock is desired, in addition to changing a configuration of the PLL (first PLL), the configuration of the second PLL is also changed to cause the frequency of the output clock to change quickly. In various embodiments, the configuration of the second PLL is changed by changing the divisor of the feedback divider of the second PLL, the divisor in a pre-scaler in the second PLL, the control voltage of a VCO used in the second PLL, and any other point of user control in the second PLL.

An oscillator includes a first resonator element, a circuit element configured to oscillate the first resonator element to generate an oscillation signal, a first package which includes a substrate, and has a housing space configured to house the first resonator element and the circuit element at one principal surface side of the substrate, a second resonator element which is disposed at another principal surface side of the substrate, and an oscillation frequency of which is controlled based on the oscillation signal, and a leg part which is disposed at the another principal surface side of the substrate, and which is arranged so as to surround the second resonator element in a plan view of the substrate.

The present invention relates to a frequency modulation method based on a phase-locked loop capable of performing fast modulation independent of bandwidth. A frequency modulation system based on a phase-locked loop capable of performing fast modulation independent of bandwidth according to the present invention includes a loop filter including a proportional path and an integral path to determine a bandwidth of a phase-locked loop, a voltage-controlled oscillator configured to adjust a frequency according to an output of the loop filter, and a slope alternator configured to alternate an input current of the loop filter, wherein the slope alternator is located in the integral path of the loop filter to generate an offset current at a moment of change from a modulation rise to a modulation fall.

In some examples, a circuit includes a clock divider and a calibration circuit coupled to the clock divider. The clock divider includes digital-to-time converter (DTC). The calibration circuit configured to determine a gain error and a parametric integrated nonlinearity (INL) error of the DTC, determine a gain adjustment value and a INL adjustment value to compensate for the gain error and the INL error, and modify operation of the DTC according to the gain adjustment value and the INL adjustment value to correct for the gain error and the INL error.

A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.

Embodiments herein relate to a phase-locked loop (PLL) circuit which compensates for varying delays in a feedback clock signal which are caused by the use of fractional division. In one aspect, a delay circuit is used to provide progressively larger delays for the feedback clock signal within each division cycle, when the divider uses the smaller divisor, N. This compensates for the associated larger frequency and smaller clock cycle, compared to when the divisor is N+1. Additionally, the delays introduced by the delay circuit can be controlled by an adaptive gain circuit. The adaptive gain circuit samples a phase error of a phase detector of the PLL to determine whether to increase or decreases the gain, thereby increasing or decreasing, respectively, the delay.

Embodiments included herein are directed towards a fractional feedback divider circuit and associated method. The circuit may include a programmable feedback divider including a plurality of flip-flops arranged in series. The programmable feedback divider may be configured to receive an input clock signal and a reset signal comprising at least one pulse and to generate a divided clock. The circuit may include reset logic configured to receive an input from the programmable feedback divider and to generate a reset signal. The circuit may include a first D flip-flop configured to receive the reset signal and to generate an output and a second D flip-flop configured to receive the output from the first D flip-flop and to generate a second output. The circuit may further include a multiplexer configured to receive the second output and to generate an output clock signal.