A signal generator includes a first phase-locked loop (PLL) configured to receive a first reference signal having a first reference frequency and generate a ramping signal based on the first reference signal, where the ramping signal is between a minimum frequency and a maximum frequency of a radar frequency band; a system clock configured to generate a second reference signal having a common system reference frequency; and a second PLL configured to receive the second reference signal from the system clock, generate the first reference signal based on the second reference signal, and provide the first reference signal to the first PLL.

A phase and amplitude controlled oscillation device is configured in such a manner that a first controller and a second controller control a phase of a combined output wave obtained by a combiner by performing control to shift phases of respective oscillation frequencies of a first oscillator and a second oscillator in the same direction, and control an amplitude of the combined output wave obtained by the combiner by performing control to shift the phases of the respective oscillation frequencies of the first oscillator and the second oscillator in opposite directions.

A phase and amplitude controlled oscillation device is configured in such a manner that a first controller and a second controller control a phase of a combined output wave obtained by a combiner by performing control to shift phases of respective oscillation frequencies of a first oscillator and a second oscillator in the same direction, and control an amplitude of the combined output wave obtained by the combiner by performing control to shift the phases of the respective oscillation frequencies of the first oscillator and the second oscillator in opposite directions.

A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

Described herein is a method and apparatus for a multi-beam digital system including a frequency reference device having an output for providing a frequency reference signal; a fanout device connected to the frequency reference device and configured to generate n frequency reference signals from the frequency reference signal output from the frequency reference device, having n outputs configured to output the n frequency reference signals, respectively, where n is a positive integer; n local clock domain devices configured to synchronize the n frequency reference signals and distribute reference and clock signals having deterministic phase and phase/data alignment; and n beamforming devices connected to the n local clock domain devices, respectively, and configured to form a user-definable beam, and having n input configured to receive n radio frequency (RF) signals, and n outputs for transmitting n RF signals.

A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

A device includes a voltage converter and an analog to digital converter (ADC). The voltage converter includes an input to receive a first voltage and an output to output a second voltage based on a switching signal having a first discrete converter frequency and a second discrete converter frequency. The ADC is coupled to and proximate to the voltage converter. The ADC includes a digital filter configured to substantially attenuate a first filter frequency and a second filter frequency. The voltage converter further includes a frequency control device configured to set the first discrete converter frequency and the second discrete converter frequency so that the first discrete converter frequency is approximately equal to the first filter frequency and the second discrete converter frequency is approximately equal to the second filter frequency.

A device includes a voltage converter and an analog to digital converter (ADC). The voltage converter includes an input to receive a first voltage and an output to output a second voltage based on a switching signal having a first discrete converter frequency and a second discrete converter frequency. The ADC is coupled to and proximate to the voltage converter. The ADC includes a digital filter configured to substantially attenuate a first filter frequency and a second filter frequency. The voltage converter further includes a frequency control device configured to set the first discrete converter frequency and the second discrete converter frequency so that the first discrete converter frequency is approximately equal to the first filter frequency and the second discrete converter frequency is approximately equal to the second filter frequency.

Frequency synthesizers having reduced phase noise and a small step size. One example can provide frequency synthesizers having low phase noise by eliminating dividers in a feedback path and instead employing frequency converters, such as mixers. Step size can be further reduced by providing frequency converters in a reference signal feedforward path. Acquisition time can be decreased by employing a fast-acquisition phase-locked loop that is switched out after acquisition in favor of a low phase-noise phase-locked loop. Another example can reduce phase noise by employing a YIG oscillator. To improve acquisition time, a first, faster phase-locked loop can be used to lock to a signal before switching to a second, slower phase-locked loop that includes the YIG oscillator. Another example can provide low noise by including phase-locked loops that operate in a frequency range having low thermal noise while a frequency of an output signal varies over a wide range.