The present disclosure describes aspects of current removal for digital-to-analog converters (DACs). In some aspects, a circuit for converting a digital input to an analog output includes a first resistor ladder having first resistors connectable to respective current sources and connected to a first output of the circuit. The circuit also includes second resistor ladder having second resistors connectable to the respective current sources and connected to a second output of the circuit. A common node is formed between common resistor terminals of the first resistor ladder and the second resistor ladder. Current removal circuitry is connected to the common node and referenced to an amount of current provided by the respective current sources. By removing current from the common node of the resistor ladders, common-mode current at outputs of the circuit can be reduced with minimal degradation of differential performance of the circuit.

A method may include processing an analog input signal to generate a first digital signal in accordance with a first analog gain, processing the analog input signal to generate a second digital signal in accordance with a second analog gain, and generating a digital output signal of the processing system from one or both of the first digital signal and the second digital signal based on a magnitude of the analog input signal and setting the first analog gain based on the magnitude of the analog input when the digital output signal is generated from the second digital signal.

An image sensor may contain an array of imaging pixels. Each pixel column outputs signals that are read out using a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include at least first and second input sampling capacitors, a comparator, a capacitive digital-to-analog converter (CDAC), and associated control circuitry. If desired, the SAR ADC may include a bank of more than two input sampling capacitors alternating between sampling and conversion. The first capacitor may be used to sample an input signal while conversion for the second capacitor is taking place. Prior to conversion, an input voltage of the comparator and an output voltage of the CDAC may be initialized. During conversion of the signal on the first capacitor, the first capacitor is embedded within the SAR ADC feedback loop to prevent charge sharing between the input sampling capacitor and the CDAC, thereby mitigating potential capacitor mismatch issues.

It is an object of the present invention to provide a technique for reducing the variation of a bias voltage.

An analog-to-digital converter comprises a comparator including a first amplifier and a second amplifier inputted one output of the first amplifier. The first amplifier is a differential type of amplifier, and includes one input terminal for receiving a signal and the other input terminal for receiving a reference signal which changes with a predetermined slope. The second amplifier is a single-ended type amplifier, and determines an auto zero voltage based on the amplified voltage by an auto zero operation of the first amplifier and includes a self-bias circuit using the auto zero voltage as a bias voltage. The comparator is plural, the comparators are plurality which arranged in a row direction, and outputs a digital value based on an analog voltage inputted to the other input terminal in parallel operation.

One example described herein includes the digital image sensor having a pixel cell with a photodiode and a quantizer circuit coupled to the pixel cell. The quantizer circuit includes a charge storage device that generates a voltage based on electric charge from the photodiode. The quantizer circuit also includes a single-input comparator that can switch from a first output state to a second output state in response to a ramp signal provided by a ramp generator. The quantizer circuit further includes a memory switch that can cause a counter value from a digital counter to be stored in a digital memory in response to the single-input comparator switching from the first output state to the second output state. The counter value can serve as a digital pixel value associated with the pixel cell.

An analog to digital converter temperature compensation system comprising a comparator configured to compare an analog input signal to a compensated feedback signal and generate a comparator output. A SAR module processes the comparator output to generate a digital signal. A digital to analog converter, biased by a biasing signal having temperature change induced error, is configured to convert the digital signal to a feedback signal and a detector is configured to detect a signal that is proportional to temperature. A look-up table is configured to receive and convert the signal that is proportional to temperature to a compensation signal such that the compensation signal compensates for the temperature change induced error in the biasing signal. A summing node combines the feedback signal with the compensation signal to create a compensated feedback signal.

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

An apparatus includes a comparator. The comparator includes a plurality of pregain stages, and a switch network coupled to the plurality of pregain stages. The comparator further includes a latch coupled to the plurality of pregain stages.

One or more embodiments of a successive approximation type analog-to-digital converter that converts an analog input into a digital conversion value and outputs the digital conversion value, may include: a capacitance DAC that generates a bit-by-bit potential based on an analog input; a comparator that compares the potential generated by the capacitance DAC, wherein the comparator is a memory cell rewriting type, the comparator includes a first stage current mirror type operational amplifier; and a second stage memory cell; a conversion data generator that generates conversion data of resolution bits based on a comparison result of the comparator; and a correction circuit that corrects an output error of the conversion data caused by an offset error of the comparator by adding or subtracting an offset correction value that is a fixed value, and outputs the conversion data as a digital conversion value.

A sensor arrangement for light sensing for light-to-frequency conversion. The sensor arrangement includes a photodiode, an analog-to-digital converter (ADC) operable to perform a chopping technique in response to a first clock signal (CLK1), and convert a photocurrent (IPD) into a digital comparator output signal (LOUT). The ADC includes a sensor input coupled to the photodiode, an output for providing the digital comparator output signal (LOUT), an integrator including an integrator input coupled to the sensor input and operable to receive an integrator input signal, a first set of chopping switches coupled to a first amplifier, a second set of chopping switches electrically coupled to an output of the first amplifier and electrically coupled to input terminals of a second amplifier, and an integrator output providing an integrator output signal (OPOUT).