Disclosed is an input impedance boosting apparatus. More particularly, an input impedance boosting apparatus including an analog-to-digital converter; an input capacitor connected to an input terminal of the analog-to-digital converter and a ground line and including a first shielding metal formed thereunder; a feedback capacitor connected onto a positive feedback loop of the analog-to-digital converter and including a second shielding metal formed thereunder; and an impedance booster connected to both ends of the feedback capacitor and configured to boost an input impedance based on a first parasitic component formed between the input capacitor and the first shielding metal and a second parasitic component formed between the feedback capacitor and the second shielding metal is provided.

A buffer circuit includes a first differential signal input, a second differential signal input, a first source follower circuit, and a second source follower circuit. The first source follower circuit includes a first signal output, and a first input transistor. The first input transistor is coupled to the first differential signal input, and is configured to drive the first signal output. The second source follower circuit includes a second signal output, a second input transistor, and a cascode transistor. The second input transistor is coupled to the second differential signal input, and is configured to drive the second signal output. The cascode transistor is coupled to the second input transistor and the first signal output, and is configured to compensate for non-linearity of the second input transistor based on an output signal provided at the first signal output.

Provided is a potential measurement device including: a first substrate having read electrodes arranged in a two-dimensional array; and a second substrate on which the first substrate is stacked, in which each of the read electrodes includes at least one or more AD conversion circuits each having independent correspondence to the read electrode, and at least a part of the AD conversion circuits is arranged in a two-dimensional array on the second substrate.

A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2.sup.(K+1) steps, each of which has a value equal to an integer multiplying 2.sup.(−K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2.sup.(K+1) number of N-bit digital signals based on the at least 2.sup.(K+1) steps of the digitally controlled offset voltage, summing the at least the 2.sup.(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.

In one embodiment, a femtowatt sensitivity optical detector is provided using one or more photodiodes, intended as a replacement for the photomultiplier based photon counting unit.

The present invention discloses a digital-to-analog conversion apparatus having current source measuring mechanism. A digital-to-analog conversion circuit in turn sets one of thermo-controlled current sources as an initial current source to operate according to two specific input codewords included in an input digital signal to generate an output analog signal. The values of the output analog signal corresponding to the two specific input codewords have opposite signs and the same absolute value. An echo transmission circuit processes the output analog signal to generate an echo signal. An echo-canceling circuit processes the input digital signal according to echo-canceling coefficients to generate an echo-canceling signal and receives an error signal to converge the echo-canceling coefficients. A current calculating circuit generates converged coefficients statistics values and perform calculation thereon with a predetermined inverse matrix to generate a current amount of each of the thermo-controlled current sources. An error calculation circuit subtracts the echo signal and the echo-canceling signal to generate the error signal.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for implementing a SAR ADC circuit with improved quantization error. In some implementations, an apparatus includes an analog-to-digital converter (ADC) configured to receive a set of voltage signals and generate digital representations of signals. The ADC comprises a capacitive digital-to-analog converter (CDAC) comprising a capacitive divider circuit, the capacitive divider circuit comprising (i) a first capacitor in parallel with a second capacitor in a first branch, (ii) a plurality of capacitors in a plurality of other respective branches, and (iii) the CDAC configured to receive the set of sampled voltages and adjust each set of the sampled voltages by a first voltage or a second voltage through selection of one or more capacitors of the (i) first capacitor and the second capacitor and (ii) one or more of the plurality of capacitors.

An apparatus includes a comparator. The comparator includes first and second pregain stages, and a switch network coupled to the first and second pregain stages. A plurality of switches in the switch network are operable to provide a feedback path around at least one of the first and second pregain stages. The comparator further includes a latch coupled to the second pregain stage.

Noise sources in a pipelined ADC circuit can include kT/C sampling noise from a capacitor DAC circuit and residue amplifier sampling noise. The kT/C sampling noise is inversely proportional to the size of the sampling capacitors; the larger sampling capacitors produce less noise. However, larger sampling capacitor can be difficult to drive and physically occupy significant die area. By using the described techniques, the inversely proportional relationship between the sampling noise and the size of the sampling capacitors is no longer true. The size of the sampling capacitors can be greats reduced, which can reduce the die area and reduce the power consumption of the ADC, and the kT/C sampling noise can be canceled using correlated double sampling (CDS) techniques.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.