A sample-and-hold amplification circuit can include a sampling circuit configured to sample first and second input signals in response to first and second control signals to generate first and second sampled signals, an amplification circuit configured to amplify a voltage difference between the first and second sampled signals to generate first and second output signals, and an offset compensation circuit configured to form a first path between input and output terminals of the amplification circuit in response to the first control signal to store an offset of the input terminal and form a second path between the input and output terminals in response to the second control signal to reflect the offset to the output terminal.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

The present disclosure provides digital to analog conversion circuitry comprising: a set of input nodes for receiving a digital input code; an output node for outputting an analog output signal representative of the input code; and a plurality of selectable conversion elements, wherein a parameter of each of the plurality of selectable conversion elements is configured such that a transfer function between the input code and the output analog signal is non-monotonic.

A testing device and a method for testing a device under test are provided. The testing device comprises at least two signal generators, at least two numerically controlled oscillators, at least two white gaussian noise generators, at least two digital filters, each of which comprising a respective transfer function H.sub.i, at least two adders, at least two digital-to-analog converters, and an analog processor.

An apparatus for reducing or removing a direct current (DC) offset voltage from one or more analog signals is disclosed. An analog signal may be received by an integrator. The integrator may integrate the analog signal to determine a DC offset error signal. The apparatus may integrate, invert, and amplify the DC offset error signal to provide an analog correction signal. The analog correction signal may be inverted and subtracted from the analog signal. In some implementations, the apparatus may include multiple, independent circuits to reduce or remove DC offset voltages from differential signals.

In a semiconductor integrated circuit, a first generation circuit generates a common mode voltage of a differential signal. A second generation circuit generates temperature information according to the common mode voltage. The temperature information is information corresponding to a characteristic of an amplifier circuit related to an ambient temperature. A correction circuit corrects a first reference voltage and a second reference voltage according to the temperature information. A comparator includes a first input node to which a first signal line is electrically connected; a second input node to which a second signal line is electrically connected; a third input node to which the corrected first reference voltage is input; and a fourth input node to which the corrected second reference voltage is input.

A data acquisition system (DAS) for processing an input signal from a resistive sensor (e.g., Hall effect sensor) includes a sensor signal path that digitizes the input signal. An input impedance of the sensor signal path attenuates the input signal. A gain error corrector applies a gain error correction factor in a digital domain of the DAS to the digitized input signal to compensate for a loading effect to the resistive sensor. The sensor signal path includes an inverting amplifier that provides low distortion for the input signal and an ADC (e.g., delta-sigma, SAR, pipelined, auxiliary) that digitizes the input signal. A sensor characterization path digitizes the sensor resistance which the gain error corrector uses, along with the inverting amplifier input impedance, to calculate the gain error correction factor.

A disclosed comparator includes a comparison circuit that performs comparison between an input signal and a reference signal and changes a level of a signal to be output to a first node in accordance with a result of the comparison; and a positive feedback circuit including an amplifier unit that includes a current source load and outputs a signal in accordance with a potential of the first node to a second node and a feedback unit that positively feeds back a signal in accordance with a potential of the second node to the first node. The feedback unit includes a first transistor to which output of the amplifier unit is fed back and a switch that controls turning on or off of the first transistor.

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

An analog-to-digital converter circuit includes: a first operation amplifier suitable for comparing a ramp voltage and a voltage to be converted so as to produce an amplification result and outputting the amplification result; a second operation amplifier suitable for comparing the amplification result transferred to a first input terminal with a reference voltage transferred to a second input terminal so as to produce a comparison result and outputting the comparison result; a leakage current measurer suitable for measuring a leakage current to the first input terminal; and a leakage current generator suitable for causing a current of the same amount as that of the leakage current measured by the leakage current measurer to flow to the second input terminal.