An example apparatus is disclosed for alias rejection through charge sharing. The apparatus includes a filter-sampling network, a digital-to-analog converter, and a charge-sharing switch. The filter-sampling network includes a capacitor and a first switch, which is coupled between an input node and the capacitor. The filter-sampling network is configured to connect or disconnect the capacitor to or from the input node via the first switch. The digital-to-analog converter includes a capacitor array and a second switch, which is coupled between the input node and the capacitor array. The capacitor array is coupled between the second switch and a charge-sharing node. The digital-to-analog converter is configured to connect or disconnect the capacitor array to or from the input node via the second switch. The charge-sharing switch is coupled between the charge-sharing node and the capacitor and is configured to connect or disconnect the capacitor to or from the digital-to-analog converter.

An electronic apparatus includes: a processor; a first electronic circuit that outputs a pulse width modulation signal; a low-pass filter circuit that outputs a voltage based on the pulse width modulation signal; a second electronic circuit that outputs an analog signal by using the output voltage of the low-pass filter circuit; and a third electronic circuit that converts the analog signal into a digital signal, and the processor sets a frequency of the pulse width modulation signal to a frequency at which a noise component included in the digital signal is reduced in relation to a sampling frequency of the third electronic circuit.

The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.

An N-bit type charge redistribution analog-to-digital conversion device includes an input terminal configured to receive an input signal and coupled via a line to an output terminal. The output terminal is configured to be coupled to a comparator. The device further includes three reference potential sources of different values and a network of capacitors, where a first terminal of each capacitor is coupled to the line, and where a second terminal of each capacitor is coupled to switching circuit configured for coupling the second terminal of each capacitor to one of the reference potentials.

Provided is a signal processing system including: an adaptive decimation filter apparatus which has a decimation filter which outputs an output signal obtained by down-sampling an input signal, and an aliasing noise detection unit which detects a magnitude of aliasing noise, which is folded back to a frequency lower than a Nyquist frequency in the output signal of the decimation filter by the down-sampling; and a signal processing apparatus which has a filter control unit which adjusts an order of the decimation filter on the basis of the magnitude of the aliasing noise, and an adaptive filter unit which performs filter processing on the output signal of the decimation filter.

An array-based Compressed sensing Receiver Architecture (ACRA) includes an antenna array with two or more antennas connected to two or more ADCs that are clocked at two or more different sampling rates below the Nyquist rate of the incident signals. Comparison of the individual aliased outputs of the ADCs allows for estimation of signal component characteristics, including signal bandwidth, center frequency, and direction-of-arrival (DoA). Multiple digital signal processing (DSP) techniques, such as sparse fast Fourier transform (sFFT), can be employed depending on the type of detection or estimation.

Residue generation systems for use in continuous-time and hybrid ADCs are disclosed. An example residue generation system includes at least one stub filter, configured to generate a modified analog input based on an analog input, and a quantizer, configured to generate a digital input to a feedforward DAC based on the modified analog input generated by the filter. The feedforward DAC is configured to generate a feedforward path analog output based on the digital input generated by the quantizer, and the system may further be configured to generate a residue signal based on the feedforward path analog output. Providing one or more stub filters that filter the analog input before it is quantized by the quantizer advantageously allows blockers to be attenuated before they are sampled and aliased by the quantizer.

An example apparatus is disclosed for alias rejection through charge sharing. The apparatus includes a filter-sampling network, a digital-to-analog converter, and a charge-sharing switch. The filter-sampling network includes a capacitor and a first switch, which is coupled between an input node and the capacitor. The filter-sampling network is configured to connect or disconnect the capacitor to or from the input node via the first switch. The digital-to-analog converter includes a capacitor array and a second switch, which is coupled between the input node and the capacitor array. The capacitor array is coupled between the second switch and a charge-sharing node. The digital-to-analog converter is configured to connect or disconnect the capacitor array to or from the input node via the second switch. The charge-sharing switch is coupled between the charge-sharing node and the capacitor and is configured to connect or disconnect the capacitor to or from the digital-to-analog converter.

Example embodiments relate to sensor readout systems and sensor readout methods. One example sensor readout system includes a signal generator configured to generate a biasing signal. The sensor readout system also includes a first chopper configured to modulate the biasing signal using a chopping signal with a chopping frequency f.sub.chop to generate a modulated biasing signal. Additionally, the sensor readout system includes a Wheatstone bridge circuit that includes resistive branches. At least one of the resistive branches includes an impedance-based sensor. The Wheatstone bridge circuit is configured to receive the modulated biasing signal and to generate a sensing signal based on the modulated biasing signal. Further, the sensor readout system includes a second chopper configured to modulate the sensing signal using the chopping signal with the chopping frequency f.sub.chop to generate a modulated sensing signal.

A circuit configured to: generate a reference clock signal; generate an excitation signal at a target frequency having a period that is a first integer number of cycles of the reference clock signal; update a driver circuit at an update frequency having a period that is a second integer number of cycles of the reference clock signal; digitize sense signals resulting from the excitation signal at a frequency having a period that is a third integer number of cycles of the reference clock signal; identify a fourth integer number of sense signal samples; optionally utilize an excitation control signal having a period that is a fifth integer number of cycles of the reference clock signal; and minimize harmonics at the target frequency of the excitation signal based on the first integer number, the second integer number, the third integer number, the fourth integer number, and possibly the fifth integer number.