An apparatus for determining one or more calibration values of an ADC is configured to receive a first reference signal and a second reference signal and apply to the ADC the following: over a first signal application period, a first ADC input signal including the first reference signal; over a second signal application period, a second ADC input signal having a substantially equal magnitude and an inverse polarity to the first ADC input signal; over a third signal application period, a third ADC input signal including the second reference signal; and over a fourth signal application period, a fourth ADC input signal having a substantially equal magnitude and an inverse polarity to the third ADC input signal. The apparatus is configured to determine the one or more calibration values based, at least in part, on an ADC output signal of the ADC over the four signal application periods.

An image sensing system includes a pixel array, an analog-to-digital converter circuit, and an average calculator. The analog-to-digital converter circuit converts a first pixel signal to first pixel data and converts a second pixel signal to second pixel data. The average calculator generates a first average bit based on a first bit of the first pixel data and a first bit of the second pixel data during a first time and generates a second average bit based on a second bit of the first pixel data and a second bit of the second pixel data during a second time.

A method for reducing noise in a read signal due attributable to read element asymmetry provides for transmitting a write signal through a write precompensation circuit that shifts rising edges and falling edges of each of pulse in the write signal by a select magnitude and in opposite directions. After the write signal is encoded on a media, a corresponding read signal is read, with a read element, from the media. The method further provides for transmitting the read signal through a magnetoresistive asymmetry compensation (MRAC) block that is tuned to correct second-order non-linearities characterized by a particular set of distortion signatures. The select magnitude of the waveform shift applied by the write precompensation circuit introduces a non-linear signal characteristic that combines with non-linear signal characteristics introduced by the read element to generate one of the particular distortion signatures that is correctable by the MRAC block.

We disclose an apparatus for determining one or more calibration values of an ADC, the apparatus configured to receive a first reference signal and a second reference signal and apply to the ADC the following: over a first signal application period, a first ADC input signal comprising the first reference signal; over a second signal application period, a second ADC input signal having a substantially equal magnitude and an inverse polarity to the first ADC input signal; over a third signal application period, a third ADC input signal comprising the second reference signal; and over a fourth signal application period, a fourth ADC input signal having a substantially equal magnitude and an inverse polarity to the third ADC input signal, the apparatus configured to determine the one or more calibration values based, at least in part, on an ADC output signal of the ADC over the four signal application periods.

An analog-to-digital converting device includes N-stage first analog-to-digital converters (ADCs), a second ADC, a first calibration circuit, a data recovery circuit and an output circuit. The N-stage first ADCs has a first sampling frequency that is (N+1)/N times of a second sampling frequency, and converts an input signal into first quantized outputs. The second ADC has the second sampling frequency, and converts the input signal into a second quantized output. The first calibration circuit calibrates offsets of the first quantized outputs and the second quantized output to generate third quantized outputs and a fourth quantized output. The data recovery circuit outputs, by the second sampling frequency, one of the third quantized outputs as a fifth quantized output, and subtracts the fifth quantized output from the fourth quantized output to generate output data. The output circuit generates an output signal according to the third quantized outputs and the output data.

The present invention discloses a DAC method having signal calibration mechanism used in a DAC circuit having thermometer-controlled current sources generating an output analog signal according to a total current thereof and a control circuit. Current offset values of the current sources are retrieved. The current offset values are sorted to generate a turn-on order, in which the current offset values are separated into current offset groups according to the turn-on order, the signs of each neighboring two groups being opposite such that the current offset values cancel each other when the current sources turn on according to the turn-on order to keep an absolute value of a total offset not larger than a half of a largest absolute value of the current offset values. The current sources are turned on based on the turn-on order according to a thermal code included in an input digital signal.

An AD converter includes: an accumulation conversion unit that performs a comparison of magnitudes of an input voltage V2 and an accumulated voltage V1 obtained by accumulating a unit voltage and outputs a comparison signal representing a result of the comparison; an accumulation comparison determination unit that repeatedly compares an accumulated voltage V1, obtained by repeating the comparison until the comparison signal changes and corresponding to an accumulated voltage V1 at which the comparison signal changes, and the input voltage V2 a predetermined number of times to determine an equivalent-state accumulation number in which a state probability that the comparison signal changes is equal to a threshold; and a control unit that determines conversion data of the input voltage using the equivalent-state accumulation number.

Amplifiers, preamplifiers, and other circuits may have registers that are assigned to store data corresponding to certain functions. When the data stored in the registers are no longer needed, the registers may be assigned to store data corresponding to other functions, such as signal acquisition. The registers can be logically grouped into a virtual memory bank. The memory bank may store new data to a first register, and move data from the first register to a second register when new data arrives. In some embodiments, these registers and memory control circuit can be implemented within a preamplifier circuit.

A semiconductor device includes an analog-to-digital converter configured to perform a process of sampling an analog input signal and a successive-approximation process, execute an AD conversion process, and output a digital output signal. The AD converter includes an upper DAC, a redundant DAC, a lower DAC, a comparator configured to compare a comparative reference voltage and output voltages of the upper DAC, the redundant DAC and the lower DAC, a control circuit configured to control successive approximations by the upper DAC, the redundant DAC and the lower DAC based on the comparison result of the comparator, and generate a digital output signal, and a correction circuit. The correction circuit includes an error correction circuit configured to correct an error of the upper bit with the redundant bit, and an averaging circuit configured to calculate an average value of conversion values of a plurality of the lower bits supplied multiple times.

A successive approximation register analog-to-digital converter (SAR ADC) with high accuracy is disclosed. Within the SAR ADC, a SAR logic circuit combines the output signal of a comparator collected during at least two successive cycles of a plurality of cycles of a search scheme of digital representation of an analog input and, accordingly, makes a one-step control for a voltage difference between a positive and a negative input terminal of the comparator. At least three capacitor network switching choices for a capacitor network of the SAR ADC are provided by the one-step control. By the one-step control, a selection between the at least three capacitor network switching choices is made according to at least two comparison results of the comparator obtained during the at least two successive cycles. In this manner, comparator noise is utilized as an additional quantization level to improve the overall ADC noise performance.