An example time-skew calibration circuit includes a plurality of first circuits, each including a first accumulator and a second accumulator. The time-skew calibration circuit further includes a plurality of second circuits, each including a first adder coupled to outputs of the first accumulator and the second accumulator, and a first subtractor coupled to the outputs of the first accumulator and the second accumulator. The time-skew calibration circuit further includes a decision circuit configured to combine an output of the first adder and an output of the first subtractor.

Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.

A successive approximation register (SAR) analog-to-digital converter includes a first capacitance digital-to-analog converter (CDAC), a first comparator configured to compare a voltage of an output signal from the first CDAC with a reference voltage, a first SAR circuit configured to control the first CDAC based on an output of the first comparator, a second CDAC to which the output signal from the first CDAC is input, a second comparator configured to compare a voltage of an output signal from the second CDAC with a reference voltage, a second SAR circuit configured to control the second CDAC based on an output of the second comparator and generate a digital signal representing a residual voltage of the output signal of the first CDAC, and a feedback circuit configured to delay the digital signal, generate a residual signal from the delayed digital signal, and output the residual signal to the first CDAC.

Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.

A successive approximation register (SAR) analog-to-digital converter includes a first capacitance digital-to-analog converter (CDAC), a first comparator configured to compare a voltage of an output signal from the first CDAC with a reference voltage, a first SAR circuit configured to control the first CDAC based on an output of the first comparator, a second CDAC to which the output signal from the first CDAC is input, a second comparator configured to compare a voltage of an output signal from the second CDAC with a reference voltage, a second SAR circuit configured to control the second CDAC based on an output of the second comparator and generate a digital signal representing a residual voltage of the output signal of the first CDAC, and a feedback circuit configured to delay the digital signal, generate a residual signal from the delayed digital signal, and output the residual signal to the first CDAC.

A method, apparatus, and energy metering system obtains mains samples of a mains power line signal, performs non-white noise (NWN) filtering of the mains power line signal, obtains adjustable clock source samples of an adjustable clock signal of an adjustable clock oscillator, determines a difference based on the mains samples and the adjustable clock source samples, adjusts an adjustable clock source frequency of the adjustable clock oscillator based on the difference, and applies the adjustable clock source frequency to an analog to digital converter (ADC) to determine a conversion rate of the ADC.

Described herein are techniques for mitigating bandwidth mismatch in time-interleaved (TI) analog-to-digital converters (ADC). The techniques described herein involve spreading the energy associated with spurious tones resulting from bandwidth mismatch across the frequency spectrum, thereby reducing the overall impact of each individual tone. In some embodiments, for example, the tones may disappear under the noise floor. Spreading the energy associated with the spurious tones can be achieved by increasing the periodicity of the phase oscillation. This, in turn, can be achieved by introducing, in the phase oscillation, artificial phase shifts in addition to the phase shifts arising due to bandwidth mismatch. In one example, increasing the periodicity of a phase oscillation from 4 phase samples to 8 phase samples can result in a reduction in the power of a tone as high as 7 dB.

In accordance with a first aspect of the present disclosure, a near field communication (NFC) device is provided, comprising: a receiver, said receiver including an analog-to-digital converter; a clipping detector configured to detect clipping of one or more signals processed by the analog-to-digital converter; and a sampling phase controller operatively coupled to the clipping detector, wherein said sampling phase controller is configured to adjust a sampling phase of the receiver based on an output of the clipping detector. In accordance with a second aspect of the present disclosure, a method of operating a near field communication (NFC) device is conceived.

An electronic device is provided. The electronic device includes a digital to analogue converter (DAC) circuitry, analogue to digital converter (ADC) circuitry, first power amplifier circuitry, second power amplifier circuitry, coupling circuitry configured to connect a transmitting path between the DAC circuitry and the first power amplifier circuitry and a receiving path between the ADC circuitry and the second power amplifier circuitry, a radio frequency (RF) switch connected to the coupling circuitry, RF processing circuitry connected to the RF switch, an antenna connected to the RF processing circuitry, calibration circuitry for calibrating an output of the ADC circuitry, memory, comprising one or more storage media, storing instructions, and one or more processors communicatively coupled to the DAC circuitry, the ADC circuitry, the first power amplifier circuitry, the second power amplifier circuitry, the coupling circuitry, the RF switch, the RF processing circuitry, the antenna, the calibration circuitry, and the memory, wherein the instructions, when executed by the one or more processors individually or collectively, cause the electronic device to generate a reference signal based on a mode of the electronic device changed from a first mode in which one of the transmitting path and the receiving path is connected to the RF processing circuitry to a second mode in which the first power amplifier circuitry and the second power amplifier circuitry are activated, in response to transmitting the reference signal through the transmitting path, obtain a target signal changed from the reference signal through the receiving path, obtain a calibration signal based on calibrating the target signal through the calibration circuitry, and based on the reference signal and the calibration signal, identify anomaly of at least one of the calibration circuitry, the transmitting path, and the receiving path.