Techniques are provided for implementing a file system format for persistent memory. A node, comprising persistent memory, receives an operation comprising a file identifier and file system instance information. A list of file system info objects are evaluated to identify a file system info object matching the file system instance information. An inofile, identified by the file system info object as being associated with inodes of files within an instance of the file system targeted by the operation, is traversed to identify an inode matching the file identifier. If the inode comprises an indicator that the file is tiered into the persistent memory, then the inode it utilized to facilitate execution of the operation upon the persistent memory. Otherwise, the operation is routed to a storage file system tier for execution by a storage file system upon storage associated with the node.

Embodiments of the present disclosure includes systems and methods for diagnosing and correcting deficiencies in operation of integrated circuits. A set of operational data of an integrated circuit is received by a network via a communication interface. A deficiency in operation of the integrated circuit is diagnosed based on the set of operational data. A correction is generated for improving operation of the integrated circuit based on the deficiency diagnosed. The correction is transmitted over the network via the communication interface to the integrated circuit.

An analog-to-digital converter can include: a charge distribution and holding module configured to sample a to-be-converted signal, and to perform subtraction on the to-be-converted signal and a target reference voltage by charge distribution, in order to generate a positive-phase output voltage and a negative-phase output voltage on a first and second electric rails, respectively; a common-mode voltage compensation module coupled with the first and second electric rails, and being configured to inject common-mode charges to compensate the distributed charges of the charge distribution and holding module, and to reduce a difference between a common-mode output voltage of the charge distribution and holding module and an expected value; and a comparator configured to provide a logic signal based on a comparison between the positive-phase output voltage and the negative-phase output voltage, where the logic signal corresponds to a target digital signal of the analog-to-digital converter.

Methods and systems are described for converting, using a first asynchronous ADC, an analog input signal to a digital output signal according to a first clock cycle, and outputting a done signal upon completion of the conversion, the first asynchronous ADC configured with a supply voltage large enough that the done signal is asserted prior to a next clock cycle with predetermined probability, generating, using a timing margin sensor comprising a programmable delay unit, a delayed done signal having a reduced timing margin, and measuring, using a dynamic voltage scaling controller, an error rate of the delayed done signal according to the next clock cycle, and adjusting the supply voltage provided to the first asynchronous ADC responsive to the measured error rate deviating from a target error rate by a predetermined threshold.

An analog-to-digital converter (ADC) circuit includes an ADC module configured to convert an analog input signal into an original digital output signal, an error detection module configured to detect overflow of the original digital output signal due to the analog input signal being out of an input dynamic range of the ADC module and determine a current state of the original digital output signal as a normal state or an error state, and a correction module configured to, in response to the current state of the original digital output signal being the normal state, output a corrected digital output signal based on the original digital output signal and, in response to the current state of the original digital output signal being the error state, output the corrected digital output signal based on a replacement output signal for replacing the original digital output signal.

An analog-to-digital converter includes a comparator configured to compare an input voltage and a conversion voltage and to generate a comparison result; a digital-to-analog converter configured to generate the conversion voltage according to a digital output signal; and a control circuit including a conversion control circuit configured to determine the digital output signal corresponding to the input voltage based on the comparison result; and a correction control circuit configured to correct an error of the digital output signal by increasing or decreasing the digital output signal based on the comparison result after the digital output signal is determined.