Various background calibration techniques to calibrate inter-stage gain, e.g., in pipelined ADCs, are described to allow open loop amplifier circuits to be used as residue amplifiers for better power efficiency. Using various techniques, a well-controlled perturbation can be injected between two conversions and the actual perturbation after a residue amplifier can be measured. By comparing the actual measurement against an expected value, the gain information of the residue amplifier can be estimated and then calibration can be applied.

A pipelined analog-to-digital converter has an analog signal input. A first input sample-and-hold circuit is connected to the analog signal input. An amplifier is connected to an output of the first input sample-and-hold circuit. A second input sample-and-hold circuit has an input connected to the analog signal input in parallel to the first input sample-and-hold circuit. An AD/DA conversion path is connected to an output of the second input sample-and-hold circuit. A first output sample-and-hold circuit has an input connected to an output of the amplifier. A second output sample-and-hold circuit has an input connected to the output of the amplifier. The amplifier, the first output sample-and-hold circuit, the second input sample-and-hold circuit, and the AD/DA conversion path are part of a converter stage and outputs of the converter stage are inputs to a following converter stage.

Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.

Disclosed is a calibration circuit and method. The circuit includes: a DAC that outputs an analog parameter and includes output parameter adjustment circuitry; a comparator that receives a reference parameter and the analog parameter; and a control circuit (with select logic) connected to the comparator and DAC in a feedback loop. During a calibration mode, the magnitude of the analog parameter is adjusted by DAC step in one direction and the feedback loop is used to perform a binary search calibration process. During an operation mode, the magnitude of the analog parameter is adjusted by DAC step in the opposite direction. The select logic selects the DAC step identified by the calibration process or the next higher DAC step as a final DAC step. The control circuit outputs a final DAC code corresponding to the final DAC step and the DAC generates a calibrated parameter based thereon.

An A/D converter includes an analog input terminal, a successive approximation A/D converter connected to the analog input terminal, the successive approximation A/D converter for generating an upper conversion result at an upper conversion result terminal, the successive approximation A/D converter having an internal D/A converter generating an internal reference voltage at an internal reference voltage terminal, and a delta-sigma A/D converter connected to the analog input terminal and the internal reference voltage terminal, the delta-sigma A/D converter for generating a lower conversion result at a lower conversion result terminal.

According to various embodiments, a multi-slope converter can have the following: an integrator circuit having a charge store; a clocked comparator; a sensor circuit having a capacitor arrangement and a charging circuit for pre-charging the capacitor arrangement, a discharging circuit; a switch arrangement and a controller circuit for actuating the switch arrangement based on a clock signal; wherein the controller circuit is set up to actuate the switch arrangement such that, alternately: in an integration cycle electrical charge is transferred from the capacitor arrangement of the sensor circuit to the charge store of the integrator circuit, and in a deintegration cycle the charge store of the integrator circuit is discharged by means of the discharging circuit, wherein after the integration cycle a residual charge remains stored in the charge store of the integrator circuit and is taken into consideration during a subsequent integration cycle.

A pipelined analog-to-digital converter has an analog signal input. A first input sample-and-hold circuit is connected to the analog signal input. An amplifier is connected to an output of the first input sample-and-hold circuit. A second input sample-and-hold circuit has an input connected to the analog signal input in parallel to the first input sample-and-hold circuit. An AD/DA conversion path is connected to an output of the second input sample-and-hold circuit. A first output sample-and-hold circuit has an input connected to an output of the amplifier. A second output sample-and-hold circuit has an input connected to the output of the amplifier. The amplifier, the first output sample-and-hold circuit, the second input sample-and-hold circuit, and the AD/DA conversion path are part of a converter stage and outputs of the converter stage are inputs to a following converter stage.

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

An electrical circuit for conditioning an analog electrical input signal into an analog electrical output signal includes a threshold circuit. The threshold circuit is configured to set a value of a conditioning parameter, under control of the analog electrical input signal and based on an electrical threshold. The threshold circuit is configured to set the conditioning parameter to, in response to the analog electrical input signal being below the electrical threshold, a first value. The threshold circuit is configured to set the conditioning parameter to, in response to the analog electrical input signal exceeding the electrical threshold, a second value different from the first value.

An A/D converter includes a capacitor DAC, a resistor DAC, a first capacitive element, and a comparator. The capacitor DAC is configured to convert high-order M bits, where M and N are integers equal to or greater than 2, and the resistor DAC is configured to convert low-order N bits. The first capacitive element is provided between the capacitor DAC and the resistor DAC, and the comparator is configured to compare an input signal voltage with a voltage output from the capacitor DAC. The resistor DAC generates and outputs a voltage by adding or subtracting a wait based on redundant bits in addition to N-bit resolution.