A circuit device includes a control circuit having a successive approximation register, a D/A conversion circuit adapted to perform D/A conversion on output data from the successive approximation register, and a comparison circuit adapted to compare an analog input signal and an output signal from the D/A conversion circuit with each other, the control circuit includes an upper limit value register and a lower limit value register adapted to respectively hold an upper limit value and a lower limit value of a conversion range, and increases the upper limit value or decreases the lower limit value in the case in which the same comparison result has been output by the comparison circuit a predetermined number of times or more.

A self-adaptive SAR ADC techniques that can increase speed and/or decrease its power consumption. In some example approaches, one or more bits from a conversion of a previous sample of an analog input signal can be preloaded onto a DAC circuit of the ADC. If the preloaded bits are determined to be acceptable, bit trials on the current sample can be performed to determine the remaining bits. If not acceptable, the ADC can discard the preloaded bits and perform bit trials on all of the bits. The self-adaptive SAR ADC can include a control loop to adjust, e.g., increase or decrease, the number of bits that are preloaded in a subsequent bit trial using historical data.

A circuit device includes a control circuit having a successive approximation register, a D/A conversion circuit adapted to perform D/A conversion on output data from the successive approximation register, and a comparison circuit adapted to compare an analog input signal and an output signal from the D/A conversion circuit with each other, the control circuit includes an upper limit value register and a lower limit value register adapted to respectively hold an upper limit value and a lower limit value of a conversion range, and increases the upper limit value or decreases the lower limit value in the case in which the same comparison result has been output by the comparison circuit a predetermined number of times or more.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.

A successive approximation register (SAR) analog-to-digital converter (ADC) comprises a comparator for generating a comparison value according to an analog signal; a SAR, coupled to the comparator, comprises N memory units, each memory unit storing a control value and the N control values being related to the comparison value, N being an integer greater than two; and a thermometer-coded DAC, which generates the analog signal and is coupled to the comparator and the SAR. The thermometer-coded DAC comprises N capacitors. The N capacitors are respectively coupled to the N memory units. The N terminal voltages of the N capacitors are respectively controlled by the N control values.

An A/D conversion circuit includes a reference voltage source to generate a calibration voltage, a multiplexer to receive an analog signal and the calibration voltage, and output the analog signal selected in a normal mode and the calibration voltage selected in a calibration mode or a self-diagnosis mode, an A/D converter to convert an output signal from the multiplexer into a digital signal, a non-volatile memory to hold the digital signal and calibration data, a digital calibration part to calibrate the digital signal in case of inputting the analog signal to the A/D converter in the normal mode based on the calibration data, and a self-diagnosis circuit to diagnose the A/D converter based on the digital signal in case of inputting the calibration voltage to the A/D converter in the self-diagnosis mode, and the digital signal stored in the non-volatile memory.

Disclosed herein are systems and methods that describe statistical estimation based noise reduction for SAR ADCs. For SAR ADCs, the conversion error can be available at the comparator input. Although a noisy 1-bit comparator may not be able to produce an accurate estimation for its input if used only once, the comparison can be repeated multiple times for a designated bit of the multi-bit SAR ADC. This can allow for the improvement of the estimation accuracy by examining the probability of the comparator output being 1 or 0. The estimation of a signal from a noisy environment using multiple trials can be cast as a classic statistical estimation issue. In one aspect of the disclosure, an optimal Bayes estimator is disclosed to achieve a low estimation error from the comparator on a designated bit of the multi-bit SAR ADC.

An ADC includes a comparator to provide a comparator output responsive to an input voltage of the ADC and a DAC output voltage; a SAR circuit including a SAR that stores an n-bit digital code that is initialized at a beginning of a conversion phase of the ADC, where the SAR circuit is to update the digital code responsive to the comparator output, where an ADC output is responsive to the digital code at an end of the conversion phase; and a DAC to provide the DAC output voltage responsive to the digital code and a reference voltage. The DAC includes an m-bit CDAC and an (nm)-bit RDAC to provide an intermediate voltage responsive to the nm least-significant bits of the digital code and the reference voltage. The CDAC provides the DAC output voltage responsive to the m most-significant bits of the digital code, the intermediate voltage, and reference voltage.

Disclosed herein are systems and methods that describe statistical estimation based noise reduction for SAR ADCs. For SAR ADCs, the conversion error can be available at the comparator input. Although a noisy 1-bit comparator may not be able to produce an accurate estimation for its input if used only once, the comparison can be repeated multiple times for a designated bit of the multi-bit SAR ADC. This can allow for the improvement of the estimation accuracy by examining the probability of the comparator output being 1 or 0. The estimation of a signal from a noisy environment using multiple trials can be cast as a classic statistical estimation issue. In one aspect of the disclosure, an optimal Bayes estimator is disclosed to achieve a low estimation error from the comparator on a designated bit of the multi-bit SAR ADC.

According to one embodiment, an A/D converter includes a successive approximation algorithm setting register that stores a plurality of successive approximation algorithms, an algorithm selection unit that selects a predetermined successive approximation algorithm from the plurality of successive approximation algorithms, a control circuit that generates a comparison value based on the selected predetermined successive approximation algorithm, a DAC that generates a comparison voltage from the comparison value, and a comparator that compares an analog input voltage with the comparison voltage. The control circuit generates a comparison value from a result of the comparison made by the comparator based on the selected predetermined successive approximation algorithm, and converts an analog input voltage into a digital signal from the result of the comparison made by the comparator the number of times equal to the number of bits of the digital signal.