An analog-to-digital converter includes a first converter stage comprising a successive-approximation-register (SAR) analog-to-digital converter (ADC), the SAR ADC being configured for voltage domain quantization, a second converter stage coupled to the first converter stage to quantize residual voltages of the voltage domain quantization, the second converter stage including a ring time-to-digital converter (TDC), and a third converter stage comprising an interpolation TDC, the interpolation TDC being coupled to the second converter stage to provide further time domain quantization.

An apparatus is disclosed for analog-to-digital conversion. In an example aspect, the apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference-crossing detector having an input and an output. The ADC also includes a ramp generator coupled between the output of the reference-crossing detector and the input of the reference-crossing detector. The ADC further includes a voltage shifter coupled between the output of the reference-crossing detector and the input of the reference-crossing detector.

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.

One embodiment provides an offset calibration circuitry configured to compensate an offset voltage of a resistive bridge sensor. The offset calibration circuitry includes a first current digital to analog converter (IDAC) coupled to a first successive approximation register (SAR), a second IDAC coupled to a second SAR and an SAR controller circuitry. The first IDAC is configured to couple to a negative voltage port of a resistive bridge sensor. The first SAR is configured to store a circuitry first digital value. The second IDAC is configured to couple to a positive voltage port of the resistive bridge sensor. The second SAR is configured to store a second digital value. The SAR controller circuitry is configured to adjust each bit of the first SAR and each bit of the second SAR based, at least in part, on an output of a comparator. The comparator is configured to compare a voltage on the negative voltage port or a voltage on the positive voltage port to a common mode voltage.

A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.

A system including a circuit, including a first preamplifier, a sampling switch, a regenerative latch, and a second preamplifier aligned in a pipelined sequence with the first preamplifier, wherein the first and second preamplifier are associated with dynamic comparator and configured to gain signal utilizing multiple cascaded gains and sample-and-hold stages including a plurality of phases.

The present disclosure provides an offset voltage correction circuit and an offset voltage correction method, including: a data obtaining module, configured to receive a data signal and a reference signal, and obtain a data indicator signal based on a comparison result of the reference signal and an offset data signal, the offset data signal being a data signal superimposed with an offset signal; a trimming enable module, configured to receive the data signal, the reference signal, the data indicator signal and an enable signal, obtain a theoretical indicator signal based on a comparison result of the data signal and the reference signal if the enable signal is of a high level, and generate an enable flag signal based on a comparison result of the theoretical indicator signal and the data indicator signal; and an offset correction module, configured to cancel the offset signal based on the enable flag signal.

In one embodiment a temperature sensor has a first sensing unit operable to provide a first pseudo-differential unipolar analog signal representing a first temperature value of a power unit, an interface circuit operable to provide a second pseudo-differential unipolar analog signal representing a second temperature value of a powered unit, a multiplexer circuit which is operable to provide a pseudo-differential unipolar multiplexed analog signal comprising the first analog signal or the second analog signal, and a first analog-to-digital converter, ADC, component operable to provide a first digital signal from the multiplexed analog signal, the first digital signal comprising a digital representation of the first analog signal or the second analog signal. Therein, the operation of the first ADC component is synchronized with a control signal designed for activating the power unit.

An apparatus for reducing or removing a direct current (DC) offset voltage from one or more analog signals is disclosed. An analog signal may be received by an integrator. The integrator may integrate the analog signal to determine a DC offset error signal. The apparatus may integrate, invert, and amplify the DC offset error signal to provide an analog correction signal. The analog correction signal may be inverted and subtracted from the analog signal. In some implementations, the apparatus may include multiple, independent circuits to reduce or remove DC offset voltages from differential signals.