A gain calibration device for an ADC residue amplifier includes a DAC and a flash ADC. The DAC is configured to convert the digital signal to an analog signal, and the DAC includes a calibration module used in the gain calibration of the ADC residual amplifier. The flash ADC is configured to generate a digital signal, the flash ADC includes a plurality of comparators, the total number of the plurality of comparators is equal to the number of output bits of the flash ADC, and the comparators are configured to be unevenly distributed in an input range.

A device for noise suppression and distortion correction of analog-to-digital converters based on deep learning that realizes effect of correcting noise and distortion of analog to digital converters. The method is applied to electronic ADCs or photonic ADCs. It utilizes the learning ability of the deep network to perform system response learning on ADCs which need noise suppression and distortion correction, establishes a computational model in the deep network that can suppress the reconstruction of noises and distorted signals, performs noise suppression and distortion correction on the signals obtained by ADCs, and thereby improves performance of the learned ADCs. The device improves the performance of the microwave photon system with high sampling precision of microwave photon radar and optical communication system.

A signal processing chain, such as an audio chain, produces an analog output signal from a digital input signal. The signal processing chain is operated by generating a first flag signal for the analog output signal and one or more second flag signals for the digital input signal. Each flag signal assumes a first level or a second level and is set to the first level when a signal from which the flag is generated has a value within an amplitude window. An amount the first flag signal for the analog output signal and the second flag signal for the digital input signal match each other may be calculated for issuing an alert flag which indicates an impaired operation of the signal processing chain.

An analog to digital converter comprises an input for receiving an analog input signal; a plurality of outputs for outputting parallel bits of a digital signal that represents said analog input signal; and a neural network layer providing connections between each of said outputs respectively, each connection having an adjustable weighting. The synapses of the neural networks may be memristors and training may use online gradient descent.

The invention discloses a multi-channel high-precision ADC circuit with self-calibration of mismatch error, belonging to the technical field of integrated circuit. The multi-channel high-precision ADC circuit with self-calibration of mismatch error comprises a gain error compensation circuit, a clock phase error compensation circuit, an N-bit analog-digital converter of M-channel, a gain error quantization circuit, a clock phase error quantization circuit and a control circuit. The multi-channel high-precision ADC circuit with self-calibration of mismatch error can automatically choose the calibration precision according to system precision and hardware overhead, and has the characteristic of low power consumption.

In one embodiment, a time-interleaved analog-to-digital convertor (ADC) system, includes an array of ADCs to sample respective analog voltages at sampling times indicated by respective clock signals and to output corresponding digital values, phase generator circuitry to provide multiple, different phase-shifted clock signals for driving the respective sampling times of the ADCs, and a clock and data recovery circuit including ADC-specific first-order loop filters to derive respective ADC-specific average phase error corrections, and a shared loop filter to derive a shared average phase error correction over the array of ADCs and wherein the phase generator circuitry is coupled to provide corrected respective ones of the phase-shifted clock signals responsively to both respective ones of the ADC-specific average phase error corrections derived by respective ones of the first-order loop filters, and the shared average phase error correction derived by the shared loop filter.

A DAC has a plurality DAC cells, and timing mismatch among the DAC cells can introduce errors in an output of a DAC. An efficient technique can be implemented to extract the timing error of a DAC cell. The technique involves a mixer to mix the timing error to DC (DC stands for direct current, where signal frequency is zero) and a VCO ADC to observe the output of the DAC cell to measure and extract the timing error. A first measurement is made using a first quadrature phase signal and a second measurement is made using a second quadrature phase signal. A difference between the first measurement and the second measurement yields the timing error of the DAC cell. Advantageously, the mixer can be integrated within a voltage-to-current converter of the VCO ADC. The timing error can be corrected in the digital domain or analog domain.

A gain calibration device for an ADC residue amplifier includes a DAC and a flash ADC. The DAC is configured to convert the digital signal to an analog signal, and the DAC includes a calibration module used in the gain calibration of the ADC residual amplifier. The flash ADC is configured to generate a digital signal, the flash ADC includes a plurality of comparators, the total number of the plurality of comparators is equal to the number of output bits of the flash ADC, and the comparators are configured to be unevenly distributed in an input range.

A self-calibrating analog-to-digital converter includes a reference signal circuit configured to provide a reference signal, an analog-to-digital converter configured to generate a first digital representation of the reference signal, a dual-slope analog-to-digital converter configured to generate a second digital representation of the reference signal, and a digital engine configured to compare the first digital representation with the second digital representation to obtain a difference and output a calibration signal to the analog-to-digital converter in response to the difference. The reference signal circuit, the analog-to-digital converter, the dual-slop analog-to-digital converter, and digital engine are integrated in an integrated circuit.

A successive-approximation-register (SAR) analog-to-digital converter (ADC) includes an analog circuit and a digital control circuit. The digital control circuit is coupled to the analog circuit. The digital control circuit includes a calibration circuit, a memory device, and an asynchronous control circuit. The calibration circuit is configured to perform a calibration operation. The memory device is coupled to the calibration circuit and stores calibration information generated by performing the calibration operation. The asynchronous control circuit is coupled to the memory device, and reads the calibration information from the memory device in an asynchronous control mode. In the asynchronous control mode, before the asynchronous control circuit performs the operations of the SAR ADC, the asynchronous control circuit removes the non-idea effects of the SAR ADC according to the calibration information.