An analog-to-digital (AD) convertor includes: an AD conversion circuit; and a correction circuit that corrects an output value of the AD conversion circuit based on a correction value, wherein the correction circuit generates a plurality of elemental correction values based on a plurality of output values which are converted values of a plurality of analog values by the AD conversion circuit, wherein the correction value is determined by an average value of remaining values obtained by removing a deviated value from the plurality of elemental correction values.

Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

An example analog-to-digital converter (ADC) comprising: sample and hold circuitry coupled to an analog input; a first sub-ADC coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; summation circuitry coupled to the sample and hold circuitry and the M-DAC; an amplifier coupled to the summation circuitry; a second sub-ADC coupled to the amplifier; and reference generation circuitry coupled to the first sub-ADC, the M-DAC, and the second sub-ADC, the reference generation circuitry including: reference voltage circuitry coupled to the M-DAC; a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor by a switch.

A source driver including: a current source that provides an approximately constant current; a channel coupled to a source electrode and including a digital to analog converters (DAC), the DAC including: a voltage source that applies an output voltage to the source electrode based on the approximately constant current provided by the current source; and a control unit having circuitry that: inputs a digital value; and terminates, based on the digital value, charging of the voltage source by the approximately constant current; and a calibration unit having circuitry that: generates a comparison between a test voltage applied by the voltage source with a target voltage; and modifies the approximately constant current based on the comparison.

An analog-to-digital (AD) convertor includes: a capacitance digital-to-analog (DA) convertor circuit; a comparator circuit coupled to the capacitance DA convertor circuit; and a calibration circuit that calculates a correction value for the AD convertor, wherein the capacitance DA convertor circuit includes a first capacitor, a second capacitor, n number of capacitors (n being integer equal to or larger than 3), each of the capacitors from first to n-th to be activated based on input digital data, wherein each of the first and second capacitors is designed for having a first capacitance value, wherein the n-th capacitor is designed for having twice the capacitance value of the (n1)-th capacitor, wherein the calibration circuit calculates the correction value based on first and second results of the AD convertor, and wherein the first result is generated using the n-th capacitor and the second result is generated using the capacitors from first to (n1)-th.

Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.

Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.

Embodiments of the present disclosure include a microcontroller with a processor, memory, and peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.

An analog-to-digital (AD) convertor includes: a capacitance digital-to-analog (DA) convertor circuit; a comparator circuit coupled to the capacitance DA convertor circuit; and a calibration circuit that calculates a correction value for the AD convertor, wherein the capacitance DA convertor circuit includes a first capacitor, a second capacitor, n number of capacitors (n being integer equal to or larger than 3), each of the capacitors from first to n-th to be activated based on input digital data, wherein each of the first and second capacitors is designed for having a first capacitance value, wherein the n-th capacitor is designed for having twice the capacitance value of the (n1)-th capacitor, wherein the calibration circuit calculates the correction value based on first and second results of the AD convertor, and wherein the first result is generated using the n-th capacitor and the second result is generated using the capacitors from first to (n1)-th.