A method and an apparatus for determining the suitability of a test delay value between comparator decisions of a comparator circuit of an asynchronous successive approximation analog/digital converter and a method for determining an optimized delay value of a comparator of an asynchronous successive approximation analog/digital converter are provided.

A conversion time and an acquisition time of an ADC can be estimated so that a speed of the ADC can be calibrated. An ADC circuit can perform M bit-trials in its conversion phase and continue performing additional bit-trials in a calibration mode. The ADC can count the number of additional bit-trials performed, e.g., X bit-trials, that occur before the next conversion phase, where additional bit-trials can be considered to be the number of available bit-trials during an acquisition time if the ADC continues performing bit-trials instead of sampling an input signal. The ADC can estimate the conversion time and the acquisition time using M and X. Then, the conversion time of the ADC can be calibrated by adjusting one or more of the comparison time, DAC settling delay, and logic propagation delay.

Systems and methods are provided for enhanced analog-to-digital conversions, particularly by allowing for an ultra-low burst error rate. Analog-to-digital conversion may be applied to an analog input via one or more conversion cycles; and performance related parameter corresponding to the analog-to-digital conversion may be assessed. A digital output corresponding to the analog input may be generated, with the generating being controlled based on the assessing of the performance related parameter. The controlling may include adjusting at least a portion of the digital output. The assessing may include determining, for at least one conversion cycle, whether a performance related condition, corresponding to the performance related parameter, occurs. The determination may be based on an outcome of a matching search performed for that conversion cycle. The determination that the performance related condition occurs may be made when the matching search fails to settle within a corresponding time period.

A signal processing circuit includes a first current sensor input, a second current sensor input, a voltage sensor input for receiving a sensor voltage, a first selection unit, a second selection unit, a current analog-digital converter (ADC), a voltage ADC, digital processing block, and a current-voltage converter. The first selection unit includes a first current input coupled to the first current sensor input, and a second current input coupled to the second current sensor input. The second selection unit includes a first voltage input coupled to the voltage sensor input and a second voltage input. The current ADC is coupled to a first current output. The voltage ADC is coupled to a voltage output. The digital processing block is coupled to outputs of the current ADC and the voltage ADC. The current-voltage converter is coupled between a second current output and the second voltage input.

A method of optimizing a quantization step size of an analog-to-digital converter (ADC) based on a number of crossbar arrays of a computing device includes: generating a first mapping relationship between the quantization step size of the ADC and a first root mean square error, the first root mean square error reflecting a quantization error and a clipping error, wherein the generating the first graph is based on use of only a single crossbar array; generating a second mapping relationship between the quantization step size of the ADC and a second root mean square error, the second root mean square error reflecting a quantization error, wherein the generating the second mapping is based on a uniform distribution of a total sum of quantization errors; and determining the quantization step size of the ADC based on the first mapping relationship and the second mapping relationship.

An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.

Power consumption of a successive-approximation type analog to digital converter is reduced. A system is provided with an analog to digital converter and a power-supply voltage generation unit. In the system provided with the analog to digital converter and the power-supply voltage generation unit, the analog to digital converter compares an analog signal with a reference signal and outputs frequency information indicating the number of times of comparison. Also, in the system, the power-supply voltage generation unit generates power-supply voltage on the basis of the frequency information output by the analog to digital converter and supplies the same to the analog to digital converter.

The resolution of a successive approximation analog-to-digital converter is varied in a wide range. Provided is a successive approximation analog-to-digital converter including a digital-to-analog converter that generates an analog voltage based on a digital code, a comparator to which the analog voltage as the output of the digital-to-analog converter is inputted, a DAC control circuit that generates the digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on the output of the comparator, a delay circuit that starts the determination of the comparator by signal transition generated by delaying the signal state change of the output of the comparator, a clock generation circuit that generates a signal starting the determination of the comparator, and a selector circuit that selects a signal generated by the delay circuit or a signal generated by the clock generation circuit to feed the selected signal to the comparator.

A circuit portion is provided which is arranged to be operable in a test mode. The circuit portion includes a Successive Approximation Register Analog to Digital Converter, SAR ADC, and an input for a reference signal. The SAR ADC is arranged to generate a feedback signal having a duty cycle representing a time taken for the SAR ADC to complete an analogue to digital conversion. The SAR ADC can carry out a comparison of a duty cycle of the reference signal with the duty cycle of the feedback signal, and can generate an output signal comprising a digital representation of the comparison of the reference duty cycle and the feedback duty cycle.

Disclosed is a bit error rate (BER) forecast circuit for successive approximation register analog-to-digital conversion. The BER forecast circuit includes an N bits successive approximation register analog-to-digital converter (N bits SAR ADC) and an estimation circuit. The N bits SAR ADC is configured to carry out a regular operation at least N times and an additional operation at least X time(s) in one cycle of conversion time, in which the N is an integer greater than 1 and the X is an integer not less than zero. The estimation circuit is configured to generate a test value according to total times the N bits SAR ADC carrying out the additional operation in Y cycles of the conversion time, in which the Y is a positive integer and the test value is related to the bit error rate of the N bits SAR ADC.