Apparatus, system and method for driving asynchronous digital-to-analog circuits are provided. An apparatus including circuitry configured to receive an analog signal, determine a comparison signal based on the analog signal, convert the comparison signal to a digital signal, generate a comparison reset signal after a preset delay, determine a final comparison signal based on the digital signal, convert the final comparison signal to a final digital signal, and output the final comparison signal. The circuitry successively approximates the digital signal using a binary search.

An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

A circuit for asynchronous clock generation is described. The circuit comprises a first comparator configured to receive an analog input signal; a second comparator configured to receive the analog input signal; and a clocking circuit coupled to the first comparator and the second comparator; wherein the clocking circuit generates a first asynchronous clock signal for the first comparator and a second asynchronous clock signal for the second comparator. A method of providing asynchronous clock generation is also described.

This invention is related to the method providing computation of the signal frequency components in an acceptable accuracy in contravention of the shifts in the phase and the magnitude information caused by asynchronous sampling of the signals in the process of asynchronous sampling of metal detectors wherein the received signal by the receiver unit (4) divided into time intervals, say timing values those are far shorter than the sampling period and correspond to nearest probable sampling of the ADC (6); providing the computation of the sine and cosine coefficients or exponents of time constant coefficients of the said timing value from previously located or dynamically generated coefficient table; resulting the elimination of the requirement of synchronous sampling and the requirement of the signal period is multiple of the sampling period.

One example discloses an analog to digital converter (ADC), including: an analog comparator configured to receive an analog input signal and in response generate a comparator output signal; a set of digital to analog converter (DAC) elements configured to receive the analog input signal; wherein the DAC elements are configured to generate an analog DAC output signal in response to a digital code and the analog input signal; wherein the comparator is configured to receive the analog DAC output signal; a feedback circuit configured to generate a first feedback signal and a second feedback signal from the comparator output signal; a controller configured to enable a first set of controller elements in response to the first feedback signal; wherein the controller configured to enable a second set of controller elements in response to the second feedback signal; and wherein the controller elements are configured to generate the digital code.

An electrical circuit for conditioning an analog electrical input signal into an analog electrical output signal includes a threshold circuit. The threshold circuit is configured to set a value of a conditioning parameter, under control of the analog electrical input signal and based on an electrical threshold. The threshold circuit is configured to set the conditioning parameter to, in response to the analog electrical input signal being below the electrical threshold, a first value. The threshold circuit is configured to set the conditioning parameter to, in response to the analog electrical input signal exceeding the electrical threshold, a second value different from the first value.

A digital signal processing circuit includes an analog gain compensator that compensates for an analog gain of a baseband signal including a plurality of component carriers (CCs) to output a compensated baseband signal; an analog-to-digital converter (ADC) that converts the compensated baseband signal into a first digital signal; a plurality of filtering circuits that generate a second digital signal from the first digital signal; and a control circuit. Each filtering circuit sequentially filters the first digital signal so that a corresponding one of the second digital signals retains one CC among the CCs, compensates for a digital gain, and a performs down-sampling. The control circuit generates an analog gain control signal for controlling the analog gain based on the second digital signals and a digital gain control signal for controlling the digital gain.

Disclosed herein is a method of operating a single slope analog-to-digital converter (ADC), which includes receiving an input signal from a sensor or a ramp signal from a ramp generator according to a state of a switch and sampling the received input or ramp signal, comparing, by a comparator, whether the sampled ramp signal is present in a predetermined input range in a state in which the ramp generator maintains an off state and outputting the comparison result, generating, by a logic part, a flag signal indicating a high or low according to the comparison result by the comparator and providing the flag signal to the ramp generator, and sampling, by the ramp generator, a reference voltage of the comparator according to the flag signal based on an off or on state.

There is disclosed in one example a communication apparatus, including: an analog data source; a digital communication interface; and an analog-to-digital converter (ADC) circuit assembly, including: an analog sample input; an input clock to provide frequency f.sub.in; a time-interleaved front end to interleave n samples of the analog sample input; and an ADC array including n successive-approximation register (SAR) ADCs, the SAR ADCs including self-clocked comparators and configured to operate at a frequency no less than

[00001]$\frac{f_{\mathrm{in}}}{n}.$