An analog-to-digital converter system includes an analog compute-in-memory and transform circuitry. The transform circuitry is (i) configured to receive one or more codes from corresponding one or more analog-to-digital converters of the analog compute-in-memory, (ii) configured to provide, responsive to receipt of the one or more codes, one or more transformed codes to digital circuitry configured to perform one or more digital operations on the one or more transformed codes, and (iii) configured to determine the one or more transformed codes in accordance with a distribution of results of the analog compute-in-memory.

In one aspect, an apparatus includes: a first feedback digital-to-analog converter (DAC) to receive a first feedback signal from a first successive approximation register (SAR) and output a first analog signal; a comparator to compare the first analog signal with a reference voltage; the first SAR to store a digital value based on the comparison and provide the first feedback signal to the first DAC; a second feedback DAC to receive a modulated quantized residual error based on the comparison and output a second analog signal; a second SAR to store a quantized residual error; and a delta-sigma modulator (DSM) to modulate the quantized residual error and provide the modulated quantized residual error to the second feedback DAC.

In some examples, a method includes applying a bias voltage to a resolver system. The method also includes receiving a sensed signal, the sensed signal varying in value based on a position of a rotary element. The method also includes attenuating the sensed signal to form an attenuated signal. The method also includes performing fault detection on the attenuated signal to detect faults in the resolver system. The method also includes processing the attenuated signal to determine the position of the rotary element.

Provided are a StrongArm comparator and an SAR ADC. The StrongArm comparator includes an input module, a latch module, a first reset unit and a shunt unit. The input module is configured to receive a pair of differential input voltages, and the latch module is configured to generate a pair of differential output voltages. Operation of the first reset unit is controlled by a first clock signal, discharging of the coupling nodes of the input and latch modules through the input module is activated by an active pulse of the first clock signal, and discharging of the coupling nodes through the shunt unit is activated by an active pulse of a second clock signal, where a leading edge of the active pulse of the second clock signal lags behind the active pulse of the first clock signal, and trailing edges of the first and second clock signals end simultaneously.

A system may include one or more receivers, circuitry, and a controller. Each of the one or more receivers may include a plurality of analog-to-digital converters (ADCs). Each ADC may measure a time relating to an analog-to-digital conversion by the ADC, compare the time with a threshold, and generate, based on a result of the comparing, a first signal. The circuitry may be coupled to the one or more receivers. The circuitry may receive the first signal from each ADC, determine, based at least on the first signal, characteristics of performance of each receiver, and output a plurality of second signals. Each of the plurality of second signals may indicate the characteristics of performance of a corresponding receiver. The controller may be coupled to the circuitry and adjust a voltage provided to the one or more receivers, based at least on the plurality of second signals received from the circuitry.

A circuit portion is provided which is arranged to be operable in a test mode. The circuit portion includes a Successive Approximation Register Analog to Digital Converter, SAR ADC, and an input for a reference signal. The SAR ADC is arranged to generate a feedback signal having a duty cycle representing a time taken for the SAR ADC to complete an analogue to digital conversion. The SAR ADC can carry out a comparison of a duty cycle of the reference signal with the duty cycle of the feedback signal, and can generate an output signal comprising a digital representation of the comparison of the reference duty cycle and the feedback duty cycle.

An electrical circuit for conditioning an analog electrical input signal into an analog electrical output signal includes a threshold circuit. The threshold circuit is configured to set a value of a conditioning parameter, under control of the analog electrical input signal and based on an electrical threshold. The threshold circuit is configured to set the conditioning parameter to, in response to the analog electrical input signal being below the electrical threshold, a first value. The threshold circuit is configured to set the conditioning parameter to, in response to the analog electrical input signal exceeding the electrical threshold, a second value different from the first value.

In described examples, an integrated circuit (IC) includes multiple subcircuits. The subcircuits include a first subcircuit that receives a current and sinks a portion of the current that is responsive to a threshold. In response to the current being greater than the threshold, the first subcircuit provides a difference between the current and the portion to a second subcircuit and asserts a signal corresponding to an ordinality of the first subcircuit. The second subcircuit is configured to repeat the actions with respect to the first subcircuit, with the second subcircuit in place of the first subcircuit and a third subcircuit in place of the second subcircuit, and with the difference in place of the current, in response to the IC comprising the third subcircuit.

An analog-to-digital converter system includes an analog compute-in-memory and transform circuitry. The transform circuitry is (i) configured to receive one or more codes from corresponding one or more analog-to-digital converters of the analog compute-in-memory, (ii) configured to provide, responsive to receipt of the one or more codes, one or more transformed codes to digital circuitry configured to perform one or more digital operations on the one or more transformed codes, and (iii) configured to determine the one or more transformed codes in accordance with a distribution of results of the analog compute-in-memory.

An integrated circuit includes an analog-to-digital converter (ADC), associated with a thermal sensor, to determine a present power supply value of a power supply voltage for the thermal sensor. E-fuse registers store a set of calibrated temperature values, from the thermal sensor, for each power supply value of a plurality of power supply values. Control logic is coupled to the ADC and the e-fuse registers. The control logic reads the present power supply value from the ADC and generates, based on the present power supply value and the plurality of power supply values, a calibration equation that relates calibrated temperature values to thermal sensor values for the present power supply value.