An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.

A method and an apparatus for determining the suitability of a test delay value between comparator decisions of a comparator circuit of an asynchronous successive approximation analog/digital converter and a method for determining an optimized delay value of a comparator of an asynchronous successive approximation analog/digital converter are provided.

A method of enhancing SAR ADC performance includes employing PVT processor to correct process, voltage and temperature (PVT) variation. The PVT processor senses process, supply voltage and temperature information then maximize the time for SAR binary search process. The PVT processor first applies coarse optimization to correct process and voltage variation then applies fine optimization to correct the temperature variation. The SAR ADC is operated at its optimized PVT condition and its performance is enhanced after PVT optimization.

A method of enhancing SAR ADC performance includes employing PVT processor to correct process, voltage and temperature (PVT) variation. The PVT processor senses process, supply voltage and temperature information then maximize the time for SAR binary search process. The PVT processor first applies coarse optimization to correct process and voltage variation then applies fine optimization to correct the temperature variation. The SAR ADC is operated at its optimized PVT condition and its performance is enhanced after PVT optimization.

A method and apparatus for calibrating a CDAC-based analog-to-digital converter is disclosed. In one aspect, a calibration method includes: applying a predetermined pattern of voltages to first plates of a group of N capacitors, wherein N is an integer greater than 1; applying a zero voltage to the second plates of the group of N capacitors, wherein the second plates of the group of N capacitors are connected in common; removing the zero voltage to the second plates of the group of N capacitors; applying a zero voltage to all of the first plates of the group of N capacitors; quantizing a voltage on the second plates of the group of N capacitors; converting the quantized voltage on the second plates of the group of N capacitors to an adjustment value; and loading the adjustment value into a lookup table.

A successive-approximation-register (SAR) analog-to-digital converter (ADC) includes an analog circuit and a digital control circuit. The digital control circuit is coupled to the analog circuit. The digital control circuit includes a calibration circuit, a memory device, and an asynchronous control circuit. The calibration circuit is configured to perform a calibration operation. The memory device is coupled to the calibration circuit and stores calibration information generated by performing the calibration operation. The asynchronous control circuit is coupled to the memory device, and reads the calibration information from the memory device in an asynchronous control mode. In the asynchronous control mode, before the asynchronous control circuit performs the operations of the SAR ADC, the asynchronous control circuit removes the non-idea effects of the SAR ADC according to the calibration information.

Multipliers are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers. Generally, digital multipliers can operate at high speed with high precision, and synchronously. As the precision and speed of digital multipliers increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes solutions unsuitable for some ML and AI segments, including in portable, mobile, or near edge and near sensor applications. The present invention discloses embodiments of multipliers that arrange data-converters to perform the multiplication function, operating in mixed-mode (both digital and analog), and capable of low power consumptions and asynchronous operations, which makes them suitable for low power ML and AI applications.

A family of current mode analog to digital converters, or TiADC, utilizing methods, circuits, and apparatuses, are disclosed with the following benefits: (1) There are normal and random non-systematic mismatch between devices in silicon manufacturing, that introduce non-linearity in current mode analog to digital converter's, or iADC, reference network. The iADC's linearity is improved by utilizing a thermometer current mode signal conditioning method, SCM. Successive applications of the SCM effectuates a segmented current reference network to function like a thermometer network, which operates based on the function of summation. Having a TiADC with a thermometer reference network, where current segments are summed or accumulated incrementally, would inherently reduce the impact of statistical distribution of component's random mismatch on the iADC's non-linearity. Accordingly, linearity of TiADC can be improved by the square root of the sum of the square of mismatch errors of the number of segmented current references in the thermometer network. (2) speed is improved by operating the TiADC in current mode, which is inherently faster. (3) voltage swings in current mode are small, which enables the iADC to operate at lower power supply voltages. (4) The TiADC can operate in subthreshold and at very low currents, which lower powers consumption. (5) the TiADC is asynchronous. Being clock free, TiADC has lower dynamic power consumption with reduces digital system noise. (6) the signal conditioning method or SCM utilized in TiADC provides concurrent functions of analog differencing and digital comparison. This trait enhances the dynamic response of iADC, wherein the digital output throughput accuracy degrades gradually and not abruptly as a function of increasing frequency of iADC's input signal. (7) No passive devices, such as capacitors or resistors, are required for the TiADC. (8) TiADC can be fabricated on low cost mainstream standard digital CMOS processes.

This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (S.sub.IN) and outputs a time-encoded output signal (S.sub.OUT). A filter arrangement (102) receives the input signal and also a feedback signal (S.sub.FB) from the TEM output, and generates a filtered signal (S.sub.FIL) based, at least in part, on the feedback signal. A comparator (101) receives the filtered signal and outputs a time-encoded signal (S.sub.PWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp (103), capacitance (104) and switch network (105). In the first mode the op-amp (103) is enabled, and coupled with the capacitance (104) to provide the active filter. In the second mode the op-amp (103) is disabled and the capacitance coupled to a signal path for the feedback signal to provide a passive filter.

Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.