A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively holds or provides the input signal value at the output for further processing without requiring switched-capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the front end sampler in a variety of analog-to-digital converters.

A low voltage drive circuit (LVDC) includes a drive sense circuit operable to convert an analog outbound data into an analog transmit signal that is transmitted on a bus, receive an analog receive signal from the bus, and convert the analog receive signal into the analog inbound data. The LVDC further includes a signal generator operable to convert transmit digital data into the analog outbound data. The LVDC a digital output circuit that includes an analog to digital converter operable to convert the analog inbound data into digital inbound data, a digital filtering circuit operable to filter the digital inbound data to produce a set of frequency domain digital data signals, and a data formatting module operable to convert the set of frequency domain digital data signals into received digital data.

Diverse applications in particle physics experiments and emerging technologies such as Lidar are driving performance increase and cost reduction in giga-hertz sampling-rate high-resolution data conversion. In applications such as these, critical aspects of the data may occur only during relatively short nanosecond portions of observation periods lasting microseconds. Data acquisition architectures that key in on regions of the data containing activity, digitize the data, and provide info to accurately measure the position of the data in time relative to a time reference are described. These architectures may facilitate system implementation and reduce overall system cost.

A control circuit for signal sampling of an analog RF signal includes: a spectrum monitoring circuit for monitoring the analog RF signal to determine a frequency of the analog RF signal; a tunable clock source for generating a tunable sampling clock for sampling the analog RF signal; a sample clock tuning circuit for controlling the tunable clock source and selecting a sample clock frequency of the tunable sampling clock that provides a predetermined ratio between the sample clock frequency of the tunable sampling clock and a center frequency of the analog RF signal; and an Analog-to-Digital Converter (ADC) for sampling the analog RF signal using the tunable sampling clock.

An A/D conversion circuit converts an analog signal into numerical data. The A/D conversion circuit includes: a pulse delay circuit that includes an odd number of delay units connected in series, and inverting and delaying a pulse signal, and that changes the numeral number of the delay units which the pulse signal passes through in accordance with a value of the analog signal; latch circuits that synchronize the pulse signal with sampling clocks, and latch the pulse signal; encoders that set a position of the pulse signal to the numerical data by circulating encode values periodically set in order from an initial value to a final value to synchronously sample the encode values; subtractors that calculate each of differences between a previous value and a current value; and an adder that adds subtraction results. The encode values are set to be shifted between at least two encoders.

Disclosed is a receiver circuit comprising an analog-to-digital converter (ADC) circuit having an analog input, a clock input, and a digital output, and a clock divider circuit having a reference clock input and a phase selector input, and having a clock output coupled to the clock input of the ADC circuit. The clock divider circuit is configured to divide a reference clock signal coupled to the reference clock input at a reference clock frequency, to produce a clock output signal at an ADC clock frequency, at the clock output, such that the reference clock frequency is an integer multiple N of the ADC clock frequency. The clock divider circuit is further configured to select from among a plurality of selectable phases of the clock output signal, responsive to a phase selector signal applied to the phase selector input.

A Lidar system and method of detecting an object is disclosed. The Lidar system includes a photodetector, a spectrum analyzer and a processor. The photodetector generates an electrical signal in response to a reflected light beam received at the photodetector, the reflected light beam being a reflection of a chirp signal from the object. The electrical signal has a bandwidth the same as a bandwidth of the chirp signal. The spectrum analyzer includes a power divider that partitions the electrical signal into a plurality of channels, an analog-to-digital converter that converts the electrical signal within a selected channel from an analog signal to a digital signal, and a comb filter that provides output from the selected channel from the power divider to the analog-to-digital converter. The processor determines a parameter of the object from the digital signal in the selected channel.

A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively holds or provides the input signal value at the output for further processing without requiring switched-capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the front end sampler in a variety of analog-to-digital converters.

Diverse applications in particle physics experiments and emerging technologies such as Lidar are driving performance increase and cost reduction in giga-hertz sampling-rate high-resolution data conversion. In applications such as these, critical aspects of the data may occur only during relatively short nanosecond portions of observation periods lasting microseconds. Data acquisition architectures that key in on regions of the data containing activity, digitize the data, and provide info to accurately measure the position of the data in time relative to a time reference are described. These architectures may facilitate system implementation and reduce overall system cost.

An analog demultiplexer circuit includes a clock distribution circuit that outputs clock signals (CK1P and CK1N) and clock signals (CK2P and CK2N) complementary thereto, a track-and-hold circuit that holds analog input signals (VINP and VINN) in synchronization with the clock signals (CK1P and CK1N), and a track-and-hold circuit that holds the analog input signals (VINP and VINN) in synchronization with the clock signals (CK2P and CK2N).