A control circuit for signal sampling of an analog RF signal includes: a spectrum monitoring circuit for monitoring the analog RF signal to determine a frequency of the analog RF signal; a tunable clock source for generating a tunable sampling clock for sampling the analog RF signal; a sample clock tuning circuit for controlling the tunable clock source and selecting a sample clock frequency of the tunable sampling clock that provides a predetermined ratio between the sample clock frequency of the tunable sampling clock and a center frequency of the analog RF signal; and an Analog-to-Digital Converter (ADC) for sampling the analog RF signal using the tunable sampling clock.

According to certain aspects, the present embodiments provide a solution for sampling and converting an analog signal at high frequencies but with low power consumption. In some embodiments, a low power, low resolution, AC coupled ADC is used to track the high frequency component of the analog input signal, in parallel with a high resolution ADC to sense the DC signal at a significantly lower sample rate. According to some aspects, the AC coupled ADC requires no reference or a low resolution reference. In these and other embodiments, a plurality of low resolution, low power ADCs having a high sampling rate may be time multiplexed together with a precision ADC at a low sampling rate.

An analog to digital converter (ADC) sampling time control method includes: grouping, by an electronic control unit, analog sensor signals received from a plurality of sensors based on a similar signal; setting, by the electronic control unit, a sampling time for converting the grouped analog sensor signals into digital signals; and obtaining, by the electronic control unit, a sensor value by converting the grouped analog sensor signals into the digital signals based on the set sampling time.

An analog-to-digital converter (ADC) module includes a plurality of frequency stacked ADCs. A splitter splits channels into two segments to transmit the signal through respective low pass and high pass filters to send the analog signal to a low frequency ADC and a high frequency ADC along each channel. When using a quad-tuner having four channels, there are eight ADCs: four high frequency ADCs and four low frequency ADCs. Typically, there is one ADC associated with each channel. Thus, a quad-tuner would be used with an ADC module having four ADCs. However, by splitting and filtering each channel and increasing the number of ADCs in the ADC module, the system, assembly, and method in the present disclosure is able to increase the frequency bandwidth throughput along legacy radio frequency (RF) cables on a platform without the need of replacing any legacy hardware or the legacy RF cables.

A report interval mode is selected from one of multiple selectable report interval modes in cases where the preferred sensor sample intervals of multiple applications are different. By using multiple selectable report interval modes some of the problems that occur when a single fixed report interval mode is used can be avoided.

A method and circuit for recovering data from a digital bitstream received from an analog to digital converter includes asynchronously oversampling the digital bitstream at a sampling rate dictated by an estimate of a clock rate of the analog to digital converter and a nominal oversampling factor. The method and circuit also includes calculating widths of bits of the digital bitstream, and calculating a learned oversampling factor using the calculated widths of a predetermined number of bits of the digital bitstream and a minimization function. The method and circuit also includes calculating data bits to be inserted to a digital filter for digestion using the calculated widths of the bits of the digital bitstream and the learned oversampling factor.

A method and system to perform the verification of measures done by a sensor in quasi real-time. The sensor verification may be implemented at two different levelsa functionality level and a measurement level. At the functionality level, a consistency check of information from different variables may be processed at sensor level depending on the functionality of the physical system being measured. At the measurement level, diagnostics may be performed of the circuits present in the measurement path by specific circuitry and at suitable instants of time to guarantee a Fault Tolerant Time Interval while minimizing sample loss. This may be achieved, at least in part, by increasing the measuring sample rate.

Embodiments herein describe a hardened fractional resampler that includes a fixed filter that supports simultaneous processing of N input samples with minimal additional combinational logic and no additional multipliers. In one embodiment, the fractional resampler is implemented in an integrated circuit using hardened circuit. The embodiments below exploit a pattern in the order filter phases in fractional resampling systems (such as a SSR resampling system) to use filter phases in a single fixed filter to process multiple input samples in parallel, where these filter phases would have been unused in previous resampling systems.

A report interval mode is selected from one of multiple selectable report interval modes in cases where the preferred sensor sample intervals of multiple applications are different. By using multiple selectable report interval modes some of the problems that occur when a single fixed report interval mode is used can be avoided.

Disclosed herein are multi-mode methods and devices for sample generation. An exemplary device for generating an output sample includes an analog-to-digital converter (ADC) for sampling a plurality of input analog signals and producing an ADC output sample. The ADC may include a ADC digital modulator including timing-critical components. A plurality of digital blocks may be coupled to the ADC digital modulator. The exemplary device may include a baseband processor for controlling a plurality of clock inputs. The plurality of clock inputs may drive the ADC digital modulator and the plurality of digital blocks. The baseband processor may be configured to operate in a plurality of modes including a first mode and a second mode. The first mode may include a first mode standby state and a first mode initial operating state. The second mode may include a second mode initial operating state and a second mode standby state.