A pipeline analog to digital converter includes a “k” number of stages and an output data register. A first stage of the “k” number of stages is configured to receive an analog differential input signal and produce a first digital output and a first single ended analog output. A second stage of the “k” number of stages is configured to receive the first single ended analog output and produce a second digital output. The output data register is configured to generate an output digital value based on the first and second digital outputs.

A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2.sup.n clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.

An ANC system is provided, including an AD converter performing an AD conversion on an external noise signal; an ANC signal generator generating an ANC signal for canceling a noise component arriving at ears of a user based on an output signal of the AD converter; a level detector detecting a level of the output signal and causes the ANC signal generator to power down in response to the level; and a zero-cross detector detecting a zero-cross timing of the ANC signal. The level detector starts measuring a time when the level is equal to or less than a first threshold value, and causes the ANC signal generator to perform a power down operation when the zero-cross timing is detected after the measured time exceeds the predetermined value, and causes the ANC signal generator to exit from the power down operation when the level exceeds a second threshold value.

Calibration of continuous-time (CT) residue generation systems can account and compensate for mismatches in magnitude and phase that may be caused by fabrication processes, temperature, and voltage variations. In particular, calibration may be performed by providing one or more known test signals as an input to a CT residue generation system, analyzing the output of the system corresponding to the known input, and then adjusting one or more parameters of a forward and/or a feedforward path of the system so that the difference in transfer functions of these paths may be reduced/minimized. Calibrating CT residue generation systems using test signals may help decrease the magnitude of the residue signals generated by such systems, and, consequently, advantageously increase an error correction range of such systems or of further stages that may use the residue signals as input.

An apparatus is disclosed for analog-to-digital conversion. In an example aspect, the apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference-crossing detector having an input and an output. The ADC also includes a ramp generator coupled between the output of the reference-crossing detector and the input of the reference-crossing detector. The ADC further includes a voltage shifter coupled between the output of the reference-crossing detector and the input of the reference-crossing detector.

An ANC system is provided, including an AD converter performing an AD conversion on an external noise signal; an ANC signal generator generating an ANC signal for canceling a noise component arriving at ears of a user based on an output signal of the AD converter; a level detector detecting a level of the output signal and causes the ANC signal generator to power down in response to the level; and a zero-cross detector detecting a zero-cross timing of the ANC signal. The level detector starts measuring a time when the level is equal to or less than a first threshold value, and causes the ANC signal generator to perform a power down operation when the zero-cross timing is detected after the measured time exceeds the predetermined value, and causes the ANC signal generator to exit from the power down operation when the level exceeds a second threshold value.

A control circuit of a pipeline analog-to-digital converter (ADC) is provided. The pipeline ADC includes a multiplying digital-to-analog converter (MDAC) which includes a capacitor. The control circuit includes six switches and two buffer circuits. The first and second switches are respectively coupled between one end of the capacitor and the first and second reference voltages. The output terminals of the first and second buffer circuits are respectively coupled to the first and second switches. The input terminal of the first buffer circuit is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The input terminal of the second buffer circuit is coupled to the fourth reference voltage through the fourth switch, or receives the control signal through the sixth switch. The first and second reference voltages are different, and the first and second switches are not turned on simultaneously.

Amplifiers can be found in pipelined ADCs and pipelined-SAR ADCs as inter-stage amplifiers. The amplifiers can in some cases implement and provide gains in high speed track and hold circuits. The amplifier structures can be open-loop amplifiers, and the amplifier structures can be used in MDACs and samplers of high speed ADCs. The amplifiers can be employed without resetting, and with incomplete settling, to maximize their speed and minimize their power consumption. The amplifiers can be calibrated to improve performance.

An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and a first analog residue signal corresponding to a difference between the first digital value and the analog input signal. An inverter based residue amplifier is configured to receive the first analog residue signal, amplify the first analog residue signal, and output an amplified residue signal. The amplified residue signal is converted to a second digital value, and the first and second digital values are combined to create a digital output signal corresponding to the analog input voltage signal.

A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2.sup.n clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.