An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current mode DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

A pipeline analog to digital converter includes converter circuitries. The converter circuitries are configured to sequentially convert an input signal to be digital codes. The converter circuitries includes a first converter circuitry and a second converter circuitry. The first converter circuitry is configured to a convert a first signal to be a first digital code in the digital codes, and generate a first residue signal according to the first signal and the first digital code. The second converter circuitry is configured to receive the first signal and the first digital code to quantize the first signal according to the first digital code, in order to generate a second digital code in the digital codes, and generate a second residue signal according to the first residue signal and the second digital code.

An error extraction method for foreground digital correction of a pipeline analog-to-digital converter including: acquiring a transmission curve of a pipeline analog-to-digital converter, and controlling an input signal to be within a sub-segment 0 of the transmission curve; during extraction of error information of an ith pipeline stage, setting a magnitude of the input signal according to Formula (I); locking the outputs of all previous-stage comparators in the i.sup.th pipeline stage of the pipeline analog-to-digital converter; and completing, according to original output code of the pipeline analog-to-digital converter, error extraction by means of adaptive iteration, stage-by-stage, sequentially from a last stage to a first stage of a pipeline. During quantization of error value, the invention performs, by means of a fitting-based adaptive algorithm, foreground extraction of a capacitance mismatch error, a gain bandwidth error, and a kickback error in each stage of the pipeline, without any additional circuit.

The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter.

In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

The present invention provides a comparator circuit applicable to a high-speed pipeline ADC. The comparator circuit includes a switch capacitor circuit, a pre-amplification circuit, and a latch circuit. The pre-amplification circuit includes a pre-amplifier, a resistance-adjustable device, two switches. The latch circuit includes a differential static latch, a first capacitor, a second capacitor, and a third switch. The transmission rates of a sampling phase and a setup phase can be increased.

Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.

Disclosed are an analog-to-digital converter (ADC), an electronic device including the ADC, and an operating method of the ADC. The ADC includes a first stage that includes a plurality of channels, generates a first sampling signal by sequentially sampling a first analog signal based on time interleaving, and generates a first digital signal and a first residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the first sampling signal, an amplifier that amplifies the first residual signal, and a second stage that includes a plurality of channels, generates a second sampling signal by sequentially sampling the amplified first residual signal based on time interleaving, and generates a second digital signal and a second residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the second sampling signal. The number of the plurality of channels included in the first stage is odd-numbered.