A signal converter includes a first converter, a second converter, a signal generator, and a controller. The first converter generates a first analog signal from a digital signal, and the second converter generates a second analog signal from the digital signal. The signal generator outputs a converted analog signal based on the first analog signal and the second analog signal. The controller generates one or more control signals to change a power supply state of at least one of the first converter and the second converter. The change in power supply state suppress even order harmonics.

In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.

A reference ripple suppression circuit adaptable to a successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of code-dependent compensation cells, each including a logic circuit and a compensation capacitor. A first plate of the compensation capacitor is coupled to receive a reference voltage to be compensated, and a second plate of the compensation capacitor is coupled to receive an output of the logic circuit performing on an output code of the SAR ADC and at least one logic value representing a bottom-plate voltage of a switched digital-to-analog converter (DAC) of the SAR ADC. (k1) of the code-dependent compensation cells are required maximally for k-th switching of the SAR ADC.

Provided is a photoelectric conversion device including: a pixel configured to generate a first signal in accordance with an incident light by photoelectric conversion; an amplifier unit configured to amplify the first signal to output a second signal; and a comparator unit configured to compare a voltage of the second signal with a voltage of a reference signal. A slope of the ramp waveform included in the reference signal can be switched between a first slope and a second slope , the reference voltage used for determining a setting of a gain in the amplifier unit or the comparator unit can be switched between a first reference voltage Vref1 corresponding to the first slope and a second reference voltage Vref2 corresponding to the second slope , and /Vref1/Vref2 is satisfied.

An AD converter includes a first DAC circuit, a second DAC circuit, a comparison circuit, a control circuit, and a control switch. The comparison circuit is connected to a first output node of the first DAC circuit and a second output node of the second DAC circuit and compares an electric potential of the first output node with an electric potential of the second output node. The control circuit controls the first DAC circuit and the second DAC circuit in accordance with a result of the comparison acquired by the comparison circuit. The control switch controls turning on and off of connection between a first input node of the first DAC circuit and a second input node of the second DAC circuit.

In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.

An image sensing apparatus comprises: a pixel unit; a generator that generates and outputs a plurality of reference signals having different slopes from each other that increase in proportion to elapsation of time; a selector that selects one of the plurality of reference signals; and an analog-to-digital converter that converts an analog signal outputted from the pixel unit of an image sensor to a digital signal using the reference signal selected by the selector, wherein the generator generates the plurality of reference signals in parallel, and in a case where an analog signal of a reset level is outputted from the pixel unit, the selector changes the reference signal selected from the plurality of reference signals each time the selected reference signal exceeds the analog signal.

In described examples, a phase measurement circuit includes a first switch coupled between a power terminal and a phase measurement output, the first switch having a first switch control terminal coupled to an up input. The phase measurement circuit includes a second switch coupled between the phase measurement output, the second switch having a second switch control terminal coupled to a down input. The phase measurement circuit includes a first capacitor coupled between the power terminal and the phase measurement output, a second capacitor coupled between the phase measurement output and a ground terminal, and a charge pump circuit having a first control input, a second control input, and a charge pump output, the first control input coupled to the up input, the second control input coupled to the down input, and the charge pump output coupled to the phase measurement output.

An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.

A motor drive system includes a MUX circuit, a DC voltage scaling circuit, a fault detection circuit, an ADC, and an FPGA. The MUX circuit selectively establishes a MUX input signal path and a MUX output signal path. The DC voltage scaling circuit measures a DC link voltage. The fault detection circuit receives the output DC link voltage and outputs one of a normal operation signal or a fault signal in response to comparing the DC link voltage to one or both of a U/V reference voltage and an O/V reference voltage. The ADC converts one or more input analog voltages into respective corresponding output digital voltages. The FPGA is in signal communication with the ADC output (ADC.sub.OUT) and the MUX circuit, and is configured to control the motor drive system based on a comparison between one or more of the output digital voltages.