An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit configured to convert an analog input signal to a digital value. The sigma-delta ADC circuit includes a loop filter circuit including at least one loop filter amplifier, a flash ADC circuit including multiple comparators, and a bias control circuit configured to change a biasing of the at least one loop filter amplifier according to outputs of the multiple comparators of the flash ADC circuit.

Apparatus, including a multiplexer, having a first output and multiple first inputs receiving analog input signals and an analog feedback signal and cycling through and selecting the signals for transfer in sequential signal groupings to the first output. The apparatus also includes an amplification circuit, having a second output and a second input connected to the multiplexer first output, that amplifies signals corresponding to the analog input signals with a selected gain so as to generate respective amplified analog signals at the second output. Circuitry selects a characteristic of the respective amplified analog signals from an initial signal grouping, feeds the characteristic back for input to the multiplexer as the analog feedback signal, selects a subsequent characteristic of the respective amplified analog signals from a subsequent signal grouping, and adjusts the amplification circuit gain so that the analog feedback signal and the subsequent characteristic have the same amplitude.

A signal processing circuit for a gyroscope apparatus is disclosed. The signal processing circuit includes a first electrode and a second electrode pairing with the first electrode. The signal processing circuit, being a negative feedback loop circuit, is configured to be connected with the first electrode and the second electrode and comprises a demodulator configured to convert a current from the first electrode into a voltage and demodulate the converted voltage to output a demodulated signal, an analog-to-digital converter configured to convert the demodulated signal from the demodulator into a digital signal, a proportional-integral-derivative controller that is connected to the analog-to-digital converter, a digital-to-analog converter configured to convert an output signal from the proportional-integral-derivative controller to an analog signal, and a modulator configured to be electrically connected with the second electrode and to be electrically connected with the digital-to-analog converter.

A clock control circuit of an ADC includes a plurality of fractional divider circuits, each including a programmable integer divider coupled to receive an enable skew signal, a clock signal, and an output integer signal to divide down the clock signal by a factor responsive to the output integer signal to generate a fractional divider signal. A delta-sigma modulator is coupled to receive a fractional modulus signal, an input integer signal, and the fractional divider signal to generate the output integer signal, which is a varying signal each cycle and having a long term average DC value substantially equal to a fractional divider ratio K. An extended gain control circuit is coupled to receive the fractional divider signal from each of the fractional divider circuits to generate a plurality of ramp clock signals with adjustable frequencies to adjust a gain setting of a ramp generator of the ADC.

A method may include processing an analog input signal to generate a first digital signal in accordance with a first analog gain, processing the analog input signal to generate a second digital signal in accordance with a second analog gain, and generating a digital output signal of the processing system from one or both of the first digital signal and the second digital signal based on a magnitude of the analog input signal and setting the first analog gain based on the magnitude of the analog input when the digital output signal is generated from the second digital signal.

A circuit configured to sense an input analog signal generated by a sensor at a first frequency and to generate an output digital signal indicative of the sensed input analog signal. The circuit includes a conditioning circuit, an ADC, a feedback circuit, and a low-pass filter. The conditioning circuit is configured to receive the input analog signal and to generate a conditioned analog signal. The ADC is configured to provide a converted digital signal based on the conditioned analog signal. The feedback circuit includes a band-pass filter configured to selectively detect a periodic signal at a second frequency higher than the first frequency and to act on the conditioning circuit to counter variations of the periodic signal at the second frequency. The low-pass filter is configured to filter out the periodic signal from the converted digital signal to generate the output digital signal.

Disclosed are a readout circuit, a signal quantizing method, a signal quantizing device, and a computer device. The readout circuit includes: a signal sampler, including a plurality of channels; a plurality of integrators, connected to the plurality of channels and having a one-to-one releationship with the plurality of channels; a signal processor, including a first operational amplifier, a sampling input of the first operational amplifier being connected to outputs of the plurality of integrators, respectively; and an analog-digital converter. An input of the analog-digital converter is connected to an output of the first operational amplifier.

A low power high bandwidth analog to digital converter system is disclosed. A first analog signal input receives an input signal. A first programmable gain amplifier receives the input signal. An analog to digital converter (ADC) is coupled to the output of the first programmable gain amplifier and samples the input signal for conversion to a digital signal. A controller is coupled to the ADC and the first programmable gain amplifier. The controller selects and enables either a reduced power mode or a power up mode for the first programmable gain amplifier and the ADC. The power up mode is selected and enabled when the input signal is to be sampled to operate the first programmable gain amplifier and the ADC to sample the input signal.

A semiconductor device has an A/D converter configured to convert an analog signal representing a current flowing in a control target into a digital signal, an overcurrent determination unit configured to, based on the analog signal, determine that an overcurrent has occurred in the control target when the current flowing in the control target has exceeded an overcurrent threshold, and determine that the overcurrent has not occurred in the control target when the current flowing in the control target has not exceeded the overcurrent threshold, a drive control signal generation unit configured to generate a drive control signal for controlling driving of the control target so that the current flowing in the control target is equal to a target current, based on a conversion result of the A/D converter, and generate the drive control signal to reduce the current flowing in the control target when the overcurrent determination unit determines that the overcurrent has occurred, and an overcurrent threshold setting unit configured to set the overcurrent threshold based on the conversion result of the A/D converter and the target current.

A ramp signal output circuit includes a first reference current source transistor to which a current is supplied from a current source, a first line connecting a gate of the first reference current source transistor and a gate of a first current source transistor, a branch point where a second line branches from the first line, a first ramp signal generation unit connected to the first current source transistor, and a second ramp signal generation unit connected to a second current source transistor, wherein the second line is connected to a gate of the second current source transistor.