The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.

An image sensor includes a pixel that includes a photoelectric conversion element converting an incident light to an electrical signal, a switch adjusting a capacitance of a floating diffusion (FD) node at which charges corresponding to the electrical signal are stored, and a readout circuit outputting an output voltage based on the FD node. An A/D converter may sample the output voltage transferred from the readout circuit through an output line respectively at a first time and a second time and generate a digital code based on a difference therebetween. A conversion gain controller may generate a conversion gain control signal by comparing the output voltage transferred from the readout circuit through the output line with a threshold voltage at a third time between the first and second times and provide the conversion gain control signal to the switch to set conversion gain of the pixel.

A pulse width modulation (PWM) digital-to-analog conversion circuit includes switches 102, 104, 114, 116 controlled by a first PWM signal, and switches 106, 108, 110, 112 controlled by a second PWM signal. A first operational amplifier (op-amp) includes a first input coupled to an output of a filter, and a second input coupled to an output of the first op-amp. During a first time period, an output of a second op-amp is coupled to an input of the filter via switches 102 and 104, and an output of a third op-amp is coupled to the output of the first op-amp via switches 114 and 116. During a second time period, the output of the second op-amp is coupled to the output of the first op-amp via switches 106 and 108, and an output of the third op-amp is coupled to the input of the filter via switches 110 and 112.

A buffer circuit for a radio frequency (RF) signal includes a single leg and a feedback mesh. The single leg is coupled between a voltage supply and ground. The single leg includes a pMOS FET and an nMOS FET, and an output terminal defined at drain terminals of the pMOS FET and the nMOS FET. The buffer circuit includes an input terminal capacitively coupled to gates of the pMOS FET and the nMOS FET. The input terminal is configured to receive the RF signal, and a buffered signal is provided on the output terminal. The feedback mesh is coupled to the output terminal and coupled to the gates of the pMOS FET and the nMOS FET. The feedback mesh includes a series-coupled inductive-resistive feedback impedance, and a resistive feedback impedance in parallel with the series-coupled inductive-resistive feedback impedance.

Apparatus, including a multiplexer, having a first output and multiple first inputs receiving analog input signals and an analog feedback signal and cycling through and selecting the signals for transfer in sequential signal groupings to the first output. The apparatus also includes an amplification circuit, having a second output and a second input connected to the multiplexer first output, that amplifies signals corresponding to the analog input signals with a selected gain so as to generate respective amplified analog signals at the second output. Circuitry selects a characteristic of the respective amplified analog signals from an initial signal grouping, feeds the characteristic back for input to the multiplexer as the analog feedback signal, selects a subsequent characteristic of the respective amplified analog signals from a subsequent signal grouping, and adjusts the amplification circuit gain so that the analog feedback signal and the subsequent characteristic have the same amplitude.

Techniques for monitoring a distortion signal of a power amplifier circuit, where the output of a distortion monitoring circuit includes little or no fundamental signal and closely represents the actual distortion of the amplifier circuit of a wired communications system. The power amplifier circuit can generate a distortion feedback signal that does not affect the power amplifier's output power capability, e.g., no inherent loss in the fundamental output of the amplifier. That is, using a distortion monitor circuit, the power amplifier circuit can resolve a distortion feedback signal from the intended output signal of the output power amplifier circuit.

A multiplying digital-to-analog converter (MDAC) includes an operational amplifier, a sampling capacitor circuit, a pre-sampling capacitor circuit, and a switch circuit. During a sampling cycle, the switch circuit connects a pre-defined voltage and reference voltages to the pre-sampling capacitor circuit, disconnects the pre-sampling capacitor circuit from an input port of the operational amplifier and the sampling capacitor circuit, disconnects an output port of the operational amplifier from the sampling capacitor circuit, and connects a voltage input to the sampling capacitor circuit. During a conversion cycle, the switch circuit connects the pre-sampling capacitor circuit to the sampling capacitor circuit, disconnects the pre-defined voltage and the reference voltages from the pre-sampling capacitor circuit, connects the pre-sampling capacitor circuit to the input port of the operational amplifier, connects the output port of the operational amplifier to the sampling capacitor circuit, and disconnects the voltage input from the sampling capacitor circuit.

An image pickup device, comprises: a pixel configured to output a signal based on a light reception amount; and an AD conversion unit. The AD conversion unit includes: an amplifier circuit configured to amplify a signal that is output from the pixel; a comparator circuit including an output node for outputting a comparison result signal generated by using an output signal from the amplifier circuit and a ramp signal; a memory configured to hold a digital value corresponding to the output signal, based on a result of the comparator circuit; a gain switching circuit configured to switch a gain of the amplifier circuit; and a ramp signal switching circuit configured to switch a slope of the ramp signal. The gain switching circuit and the ramp signal switching circuit are electrically connected to the output node.

An analog-to-digital converter (ADC) includes a first operator configured to subtract an analog value from an analog signal; an amplifier configured to amplify an output of the first selector; a filter configured to filter an output of the amplifier; a quantizer configured to generate a digital bit stream from an output of the filter; and a digital-to-analog converter (DAC) configured to output the analog value according to the digital bit stream.

The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.