An amplifier performs analog amplification on a signal I_A with a gain corresponding to a state GS and outputs the amplified signal as a signal M_A. An ADC converts the signal M_A to a digital signal and outputs the digital signal as a signal M_D. Analog comparators and a down-determination unit detect that the signal M_A exceeds a first level, and cause the state GS to transition to a state of gain of the next lower stage. Digital comparators and an up-determination unit detect that the signal M_D has been continuously lower than a second level for a predetermined period, and cause the state GS to transition to a state of gain of the next higher stage. The restoration circuit performs digital amplification on the signal M_D with a gain corresponding to the gain of the amplifier and outputs the amplified signal as a signal O_D.

A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.

Techniques to provide automatic-gain ranging for high dynamic range by including a separate S/H capacitor, segmenting the S/H capacitor into a plurality of capacitors, and determining the number of segments to use for a sample. In this manner, the size of the S/H capacitor can be changed (by adjusting the number of capacitors), which can change the amount of input voltage that produces an amount of charge. Using these techniques, the full-scale input range for a sample of the analog input signal can be adjusted automatically based on the magnitude of the sample, which can provide better resolution and/or better noise performance for that particular sample then would otherwise be possible.

A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

A programmable gain amplifier includes an operational amplifier and a resistor network coupled to the output node of the operational amplifier. The resistor network includes a first plurality of resistors coupled in series between the output node and a first network node. A second plurality of resistors is coupled in series between the first network node and a second network node. A unit resistor is coupled in parallel with the second plurality of resistors between the first and second resistor network nodes and a third plurality of resistors is coupled in parallel between the second resistor network node and a reference voltage. Each resistor of the second and third pluralities of resistors comprises a unit resistor. The third plurality of resistors contains N resistors and the second plurality of resistors contains (N?1) resistors.

An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node.

A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.

A programmable gain amplifier includes an operational amplifier and a resistor network coupled to the output node of the operational amplifier. The resistor network includes a first plurality of resistors coupled in series between the output node and a first network node. A second plurality of resistors is coupled in series between the first network node and a second network node. A unit resistor is coupled in parallel with the second plurality of resistors between the first and second resistor network nodes and a third plurality of resistors is coupled in parallel between the second resistor network node and a reference voltage. Each resistor of the second and third pluralities of resistors comprises a unit resistor. The third plurality of resistors contains N resistors and the second plurality of resistors contains (N?1) resistors.

Methods, systems, and devices for wireless communications are described. In some cases, a device may perform a first analog to digital conversion (ADC) to generate a first set of samples of a wireless signal, and may attenuate the signal according to a dynamic range. The device may then perform a second ADC on the attenuated signal to generate a second set of samples, amplify the second set of samples, output whichever set of samples is greater. In some other cases, the second ADC may determine to attenuate the wireless signal based on an input power, amplify the signal, and output the amplified samples. In some other cases, the wireless device may determine an estimated input power of the wireless signal at a number of antenna elements. The device may then determine an adjustment to gain states of low-noise amplifiers (LNA) associated with each of the number of antenna elements.

A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.