A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to the output of a multiplexor configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.

A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to the output of a multiplexor configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.

An encoder system includes a configurable detector array, wherein the configurable detector array includes a plurality of detectors. In an embodiment, the encoder system includes an application-specific integrated circuit (ASIC). The encoder system may also include a memory operable to store a partition map that defines a state for each of the plurality of detectors. In an embodiment, the memory includes a non-volatile memory. The encoder system may also include a controller, such as a microcontroller, operable to read from the memory the partition map and to adjust the partition map according to a misalignment measurement before configuring the configurable detector array. The encoder system may also include an emitter operable to generate a flux modulated by a motion object, wherein the configurable detector array is operable to receive the flux and generate respective current outputs for each of the detectors in response to the flux.

A semiconductor integrated circuit has a digital signal generator that generates a binary signal whose logic transitions at a timing according to a discharge amount of a second wiring which is discharged when multiplication data of first data stored in a memory cell and second data on a first wiring is a first logic; and a transition timing detector that detects a timing at which the logic of the binary signal transitions.

A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core, and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle.

In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

A SAR ADC and an electronic device are disclosed. The SAR ADC includes a read clock generation circuit, configured to connect to a first output terminal and a second output terminal of a dynamic comparator, and generate a read clock signal for reading a first or a second comparison result based on the first and the second comparison result received from the dynamic comparator. The invention reads the comparison result using the read clock signal generated by grabbing the output of the comparator, and can improve the overall analog-to-digital conversion speed of the SAR ADC. Further, the present invention can detect the occurrence of metastable state of the comparator by judging that the output of the comparator has no pulse, and read the comparison result based on the backup clock generated by the operating clock of the comparator.

An analog-to-digital converter (ADC) includes an analog voltage sampler having an energy storage device, such as a capacitive element, configured to charge based on an analog input voltage. A timer determines an elapsed time for the energy storage device to discharge to a predetermined value. The ADC outputs a digital value representing the analog input voltage based on the determined elapsed time.

An analog-to-digital converter (ADC) includes an analog voltage sampler having an energy storage device, such as a capacitive element, configured to charge based on an analog input voltage. A timer determines an elapsed time for the energy storage device to discharge to a predetermined value. The ADC outputs a digital value representing the analog input voltage based on the determined elapsed time.