An analog-to-digital converter has first and second comparators and an interpolation comparator. The first comparator receives an input signal and a comparison signal, and generates an output as a function of the input signal and the comparison signal. The second comparator receives the input signal and a second comparison signal (different from the first comparison signal), and generates a second output as a function of the input signal and the second comparison signal. The interpolation comparator, operatively connected to the first and second comparators, receives the first and second outputs, and generates a third output based on relative timing of the first and second outputs.

Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.

Methods and apparatus disclosed herein implement or otherwise embody a technique that compensates for cyclic position errors in encoder-based position detection, wherein the cyclic position errors arise from the presence of harmonic components in the encoder signals relied upon for position determination. Using position-domain compensation for errors arising in the encoder domain offers computational simplicity and impressive compensation performance, even when compensating for a plurality of higher harmonics in the encoder signals, e.g., third harmonic, fifth harmonic, etc. Consequently, even high-precision position monitoring or control can use relatively inexpensive types of encoders known to output encoder signals having significant harmonic components.

An interpolative divider divides an input clock signal according to a divide ratio and supplies an output clock signal. An integer divider receives the input clock signal and supplies an integer divider output signal. A phase interpolator is coupled to the integer divider and delays the integer divider output signal according to a quantization error. The phase interpolator includes first and second current sources. The first current source turns on k unit current elements during a first part of a charging cycle to charge a first capacitor to a first voltage, 0kM, k and M are integers, and k is determined by the digital quantization error. The second current source turns on k+M unit elements to charge a second capacitor during a second part of the charging cycle. The output clock signal transitions when the first voltage equals the second voltage.

Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.

An interpolative divider divides an input clock signal according to a divide ratio and supplies an output clock signal. An integer divider receives the input clock signal and supplies an integer divider output signal. A phase interpolator is coupled to the integer divider and delays the integer divider output signal according to a quantization error. The phase interpolator includes first and second current sources. The first current source turns on k unit current elements during a first part of a charging cycle to charge a first capacitor to a first voltage, 0kM, k and M are integers, and k is determined by the digital quantization error. The second current source turns on k+M unit elements to charge a second capacitor during a second part of the charging cycle. The output clock signal transitions when the the first voltage equals the second voltage.