An analog-to-digital converter (ADC) and a method are disclosed. The ADC has a quantizer. The quantizer comprises a linear-feedback shift register (LFSR), a decoder configured to provide a plurality of switch control signals at a plurality of decoder outputs, respectively, the plurality of switch control signals responsive to a LFSR value of the LFSR output; an electrical reference, the electrical reference having a plurality of reference outputs, the electrical reference configured to provide a plurality of reference levels at the plurality of reference outputs, respectively; a first switch providing a first switch output and a second switch output; and a comparator, the comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output, and the second reference input connected to the second switch output.

An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number n. The adder circuit includes sets of scaled capacitors, each capacitor connected to an n.sup.th input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2.sup.(n)*a unit capacitance (C.sub.UNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.

Digital calibration systems and related methods are disclosed for multi-stage analog-to-digital converters (ADCs). For one embodiment, a multi-stage ADC includes an initial ADC, an additional ADC, and calibration logic. The initial ADC generates an output signal and N-bit digital values that are based upon an input signal. The additional ADC receives the output signal from the initial ADC and generates M-bit digital values that are based upon the output signal. The calibration logic receives the N-bit digital values and the M-bit digital values and generates correction values. The correction values are based upon differences between maximum values and minimum values for M-bit digital values associated with different regions determined by the N-bit digital values. Digital conversion outputs for the multi-stage ADC are provided as combinations of the N-bit digital values and the M-bit digital values corrected with the correction values.

A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number n. The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an n.sup.th input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2.sup.(n)*a unit capacitance (C.sub.UNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.

An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number n. The adder circuit includes sets of scaled capacitors, each capacitor connected to an n.sup.th input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2.sup.(n)*a unit capacitance (C.sub.UNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.

A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number n. The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an n.sup.th input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2.sup.(n)*a unit capacitance (C.sub.UNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.

Methods and systems for performing analog-to-digital conversion is provided. In one example, an analog-to-digital converter (ADC) circuit comprises a leakage compensation circuit and a quantizer. The leakage compensation circuit is configured to: receive an input signal, the input signal being susceptible to a drift due to a charge leakage; receive a reference signal; and generate a leakage-compensated signal pair to compensate for the charge leakage, wherein the leakage-compensated signal pair comprises one of: (a) a leakage-compensated version of the input signal and the reference signal, (b) the input signal and a leakage-compensated version of the reference signal, or (c) a leakage-compensated version of the input signal and a leakage-compensated version of the reference signal. The quantizer is configured to perform a leakage-compensated quantization of the input signal based on the leakage-compensated signal pair to generate a digital output representing the input signal.

A system includes a central processing unit (CPU) core, and a pulse width modulator (PWM) controller configured to generate a PWM control signal having a PWM cycle. The system also includes an analog-to-digital converter (ADC), an accumulator, a sum register, and an oversampling register set. The oversampling register set is configurable by the CPU core to specify time points during each PWM cycle when the ADC is to convert an analog signal to a digital sample to produce a plurality of digital samples. The time spacing between consecutive digital samples varies among the specified time points. The accumulator accumulates digital samples from the ADC and stores an accumulated sum in the sum register. The CPU core reads the accumulated sum from the sum register, and can use the accumulated sum to calculate a metric (e.g., an average) of the digital samples.

An analog-to-digital converter circuit comprises code-shuffling circuitry, a plurality of digital-to-analog converter circuits, a plurality of difference circuits, and a plurality of latch circuits. The code-shuffling circuitry is operable to shuffle a plurality of digital codes among a plurality of its outputs. The plurality of digital-to-analog converter circuits are operable to convert a digital code on the respective one of the outputs to a corresponding one of a plurality of analog reference voltages. The plurality of difference circuits is operable to generate a respective one of a plurality of difference signals corresponding to a difference between an input voltage and a respective one of the plurality of reference voltages. The plurality of latch circuits is operable to latch a respective one of the plurality of difference signals to a corresponding one of a plurality of digital values.

An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.