A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal.

Disclosed herein is an analog-to-digital converter (ADC) for converting an input analog voltage to an output digital code, the ADC comprising a first node of the input analog voltage; nodes of a plurality of reference voltages; a plurality of comparators, inputs of each comparator being coupled to the first node and a node of a corresponding reference voltage of the plurality of reference voltages; a logic circuit block for receiving outputs of the plurality of comparators and generating the output digital code; and a voltage stabilizer, terminals of the voltage stabilizer being coupled with the first node and a node of a first reference voltage among the plurality of reference voltages.

Methods and devices are provided for circuits. One device includes an adjustment circuit having an adjustable resistor for modifying a resistance value of a resistive device, the adjustment circuit connected to an adjustment terminal of the resistive device. The resistance value of the adjustable resistor changes, when a voltage or charge on the adjustment terminal of the adjustable resistor is changed. The adjustable resistor is a phase change element with an adjusting terminal to which different voltage values are applied for adjusting a conversion device threshold value.

The invention relates to a filter circuit (200) comprising at least a first filter line (210). The first filter line (210) has a first input circuit (10), a first integration circuit (20) and a first output circuit (30). The first input circuit (10) is configured in such a way that, as a function of the value of the input signal, it converts an input signal into at least two distinguishable, first first-stage output signals and relays the first-stage output signals to the first integration circuit (20, 240) during a prescribed period of time. The first integration circuit (20) is configured to integrate the first first-stage output signals of the first input circuit (10) over the prescribed period of time and to generate a first integration signal (25). The first output circuit (25) is configured to compare the first integration signal (25) to a first output reference value and to generate a first second-stage output signal (35). The invention also relates to an appertaining filtering method.

An SAR ADC combined with a flash ADC includes a clock generator, a DAC and a comparator. The SAR ADC combined with the flash ADC further includes an SAR logic unit using a successive approximation register control to determine, while a clock signal is a first state that is either high or low, a part of digital bits of the input signal based on a signal outputted from the comparator and control the DAC to generate a first analog signal based on the first determined digital bits and a flash ADC using a flash control to determine, during a second state switched from the first state, a remaining part of the digital bits of the input signal based on the first analog signal and control the DAC to generate a second analog signal based on the second determined digital bits in the second state.

Embodiments of the present disclosure propose analog-to-digital conversion (ADC) systems particularly suitable for Light Detection and Ranging (LIDAR) implementations. An exemplary proposed ADC system is configured to determine whether an absolute value of an analog value is greater than a threshold, and, upon positive determination, assign a predetermined digital value as a digital value corresponding to the analog value, without proceeding with the analog-to-digital conversion of the analog value. Because the ADC system only proceeds with the analog-to-digital conversion, using an ADC, when the input analog value is smaller than the threshold, and otherwise the input analog value is simply assigned some predefined digital value, design complexity and power consumption of the system may be significantly reduced, compared to conventional ADCs used in LIDAR applications.

A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.

The present disclosure relates to an analog-to-digital converter (ADC) and a method for controlling an ADC. The ADC includes a plurality of quantization levels for analog-to-digital conversion. The ADC is adapted for utilizing a subset of the plurality of quantization levels for analog-to-digital signal conversion. The subset is formed by selecting at least one level to be deactivated using a greedy search method and deactivating the at least one level. The method includes using a subset of the plurality of quantization levels for analog-to-digital signal conversion, the subset being formed by selecting at least one level to be deactivated using a greedy search method and deactivating the at least one level.

A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.

The present disclosure relates to an input circuit comprising positive and negative branches, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that the source terminal of the transistor in each of the positive branch and the negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch.